G.Kleinschmidt said:
Hi Glen,
These are good points. I've thought about your circuit some more and agree that it is an improvement on approaches that do not use the current mirror, even though it adds some complexity.
I'm still concerned about the limited amount of first-stage gain one gets in front of the VAS in these circuit architectures, but recognize that no circuits are without limitations and a lot is a matter of architectural preference.
Its really a shame the the circuit with current mirrors by Randy Sloane doesn't work! Indeed, I guess the limitation placed on the gain by the resistor in both your circuit and the conventional circuit is what ends up making the VAS standing current definable. Your circuit approach appears to give the designer more flexibility in choosing the value of that gain-defining resistance. In cases where offsets among the input differential pairs can be held very small, the designer may be free to use a larger value of this resistance and still have a reasonable tolerance on the resulting VAS standing current.
Cheers,
Bob
jacco vermeulen said:
This patent by Bruce Candy of Halcro is a curious one. It is so, because it does not employ error correction of the Hawksford variety.
His earlier error correction patent, where he merely added an output-bootstrapped power supply to the Hawksford scheme, was #5,892,398. Most of us have assumed that he has based all or part of his amplifier line on this patent.
This later patent uses, instead of HEC, a high-order feedback scheme (at least third order) with enormous amounts of global as well as local feedback. I honestly don't know if he has switched to this non-HEC scheme in his later amplifiers.
It is also curious that this later patent is the first time he mentions the relevent HEC prior art, including that of Hawksford and myself. Go figure...
Cheers,
Bob
Nelson Pass said:One of the requirements of a patent is disclosure of prior art,
but I don't believe you are required to perform a search, so not
searching (or more specifically, not finding) is perhaps a functional
strategy, the patent office being what it is these days.
The requirement is that of disclosing KNOWN and RELEVANT prior art.
The Patent Office used to have a "fraud czar" to spank some of these characters that failed to report. Before I retired, I couldn't get the powers-that-be to give a damn about an inventor failing to disclose his OWN prior art. I think we should assume he knew about that. I think the Office just regards the issue as the inventor's problem if he tries to enforce any granted patent. In the mean time, our government collects a maintenance tax on the issued patent. A LOT of things changed around there when maintenance fees became a cash cow!
Nelson Pass said:One of the requirements of a patent is disclosure of prior art,
but I don't believe you are required to perform a search, so not
searching (or more specifically, not finding) is perhaps a functional
strategy, the patent office being what it is these days.
Hi Nelson,
He would not have had to perform a search. It is inconceivable that he was unaware at the time (of his earlier error-correction patent) of the work done by Hawksford and myself, which predated by about 10 years. The circuits he shows in that first patent are conspicuously similar to the earlier work, even down to the way in which the EC circuit was compensated.
Cheers,
Bob
Overhere the three criteria to apply for a patent are:
1-Novelty of the invention
2-Inventivity
3-Industrial application
No3 states that an invention has to be a functional product.
Different are : shape and label design patents, mainly the duration of the patent, validity of 14 years in the US.(author IP rights belong to a different club i think)
1-Novelty of the invention
2-Inventivity
3-Industrial application
No3 states that an invention has to be a functional product.
Different are : shape and label design patents, mainly the duration of the patent, validity of 14 years in the US.(author IP rights belong to a different club i think)
Fanuc said:
This quote from post #575
I haven't finished re-reading this thread, so I don't know if this was mentioned, but I'll add it in case it wasn't.
Cherry, in "Ironing out Distortion", EW+WW, 1/95, commented on Self's negative view of incorporation of output stage in Miller loop:
"If an amplifier oscillates when C is moved, it usually oscillates at several megahertz (far avove the frequency of unity overall loop gain) and will usually continue to oscillate if the overall feedback can somehow be removed. The oscillation is a local parasitic. Try adding capacitors of around 50pf between collector and base of the first member of the output Darlingtons, using the shortest possible leads. Try shortening all leads to the output transistors. Try a small resistor in series with C, in therory about 20% larger than the second-stage emitter-degeneration resistor."
I might add that he also stated that he always incorporates a judicious amount of emitter degeneration in the second stage (to help stability) and a properly-designed load stabilizing network, lately poo-pooed in this forum.
If one has a SPICE sim of an amp, one doesn't need to treat the problem as one person's word against another.
If simulating with LTSpice, the idea is to use the LTSpice loop gain probe, but in a slightly different way than the normal way of simulating the global loop gain of the amp. The trick is to place a very large inductor, say 1e10 H, in series with the inverting input of the power amp in the sim. This allows a correct DC operating point to be found (because global DC feedback is still there), but disables the AC global feedback even at very low audio frequencies. Then the loop gain probe is placed inside the VAS loop itself - say, with the base of the first VAS transistor on one side of the probe and the Miller cap (input side) on the other. So the VAS with Miller cap is considered to be a local feedback circuit in this way. Using this method, you can plot the loop gain of just the VAS by itself.
What you're looking for is the frequency at which the magnitude of the loop gain is 0 dB - the unity loop gain frequency of the VAS. The phase shift of the loop must be well defined up to and somewhat beyond this frequency. When I tried this with a sim of my amp, my VAS had a unity loop gain frequency of around 50 MHz. So Widlar's assertion of needing to control the phase of the loop gain out to 100 MHz looks like it's right on the money.
You can get the advantages of Cherry's approach without the stability problem with a circuit that Edmond calls TMC (transitional Miller compensation). The TMC circuit puts the output stage in the local VAS loop at audio frequencies, but it's completely removed from the VAS loop by the time the unity loop gain frequency of the VAS is reached. This ensures that the output stage doesn't degrade the stability of the VAS.
If simulating with LTSpice, the idea is to use the LTSpice loop gain probe, but in a slightly different way than the normal way of simulating the global loop gain of the amp. The trick is to place a very large inductor, say 1e10 H, in series with the inverting input of the power amp in the sim. This allows a correct DC operating point to be found (because global DC feedback is still there), but disables the AC global feedback even at very low audio frequencies. Then the loop gain probe is placed inside the VAS loop itself - say, with the base of the first VAS transistor on one side of the probe and the Miller cap (input side) on the other. So the VAS with Miller cap is considered to be a local feedback circuit in this way. Using this method, you can plot the loop gain of just the VAS by itself.
What you're looking for is the frequency at which the magnitude of the loop gain is 0 dB - the unity loop gain frequency of the VAS. The phase shift of the loop must be well defined up to and somewhat beyond this frequency. When I tried this with a sim of my amp, my VAS had a unity loop gain frequency of around 50 MHz. So Widlar's assertion of needing to control the phase of the loop gain out to 100 MHz looks like it's right on the money.
You can get the advantages of Cherry's approach without the stability problem with a circuit that Edmond calls TMC (transitional Miller compensation). The TMC circuit puts the output stage in the local VAS loop at audio frequencies, but it's completely removed from the VAS loop by the time the unity loop gain frequency of the VAS is reached. This ensures that the output stage doesn't degrade the stability of the VAS.
To chip in with one small remark regarding the previous post(s):
There is one problem with a sim: It does not take layout and track characteristics into account. My own experience in the 1 - 10 MHz region was that I had to do some on-board "calming" with small Cs and even Ls of problems not evident on Spice. Printed board track inductance can count, as can (will!) capacitances between power device and heatsink.
There is one problem with a sim: It does not take layout and track characteristics into account. My own experience in the 1 - 10 MHz region was that I had to do some on-board "calming" with small Cs and even Ls of problems not evident on Spice. Printed board track inductance can count, as can (will!) capacitances between power device and heatsink.
Hi Johan,
You're absolute right. I too always include the inductance of the leads or tracks to the O/P devices in my simulations. If the inductances are too large, Cherry's approach will inevitably fail.
BTW, I have seen some photographs of an experimental amplifier built by D. Self, showing untwisted leads, some 15cm long, to the O/P trannies. If he was trying Cherry's approach in a setup like this, no wonder that the whole thing started to oscillate.
Regards, Edmond.
Fellow designers, I am NOT trying to pick on the Creek design. It just offers an example of what to watch for in 'Stereophile' measurements or your own personal measurements.
IF you can detect ANY higher order harmonic distortion, it is a warning sign. With my designs that have predominant 2'nd or 3'rd harmonic. I have to do a FFT analysis of the THD null waveform, in order to look for 5th, 7th, 9th, etc waveforms. I personally focus on the 7th harmonic, and attempt to keep it as low as possible.
Perhaps, now you can also understand why Charles and I don't like negative feedback much, if at all. It tends to promote higher order distortion, both in its own action and in the design compromises that people make in order to use high amounts of negative feedback.
Let me assure you that 'low enough' distortion figures were made decades ago by makers of Japanese and American audio equipment. If you don't listen seriously, and only read graphs, the job was done long ago.
Still, designers keep working on making better sounding amps.
IF you can detect ANY higher order harmonic distortion, it is a warning sign. With my designs that have predominant 2'nd or 3'rd harmonic. I have to do a FFT analysis of the THD null waveform, in order to look for 5th, 7th, 9th, etc waveforms. I personally focus on the 7th harmonic, and attempt to keep it as low as possible.
Perhaps, now you can also understand why Charles and I don't like negative feedback much, if at all. It tends to promote higher order distortion, both in its own action and in the design compromises that people make in order to use high amounts of negative feedback.
Let me assure you that 'low enough' distortion figures were made decades ago by makers of Japanese and American audio equipment. If you don't listen seriously, and only read graphs, the job was done long ago.
Still, designers keep working on making better sounding amps.
Hi John,
I didn't read you as picking on Creek designs.
I guess what you are getting to is the misuse of negative feedback for numbers only.
-Chris
I didn't read you as picking on Creek designs.
Negative feedback should not be used primarily to reduce distortion. In a good design, negative feedback in smaller amounts seems to do a great job. With any luck, the design is already linear enough to avoid higher levels of high order harmonics.
I guess what you are getting to is the misuse of negative feedback for numbers only.
-Chris
