Spice simulation

[MJL21193]

Hi Andy,
You aren't talking to yourself. I, for one, am listening.
So one would just add the NK value to the existing model?

 

[andy_c]

Hi John,

It's not something the end user would ordinarily do. Model development involves writing software that implements the same equations that SPICE uses internally, along with optimization code that simultaneously adjusts a number of SPICE model parameters to get an optimum fit of simulated to measured data.

It's an inexact process that's made more uncertain by the fact that vendor datasheets don't have all the data needed by the models.

 

[PB2]

Nice work and thanks again Andy.

I seem to recall seeing larger than expected Vbe vs. Ib in a CE output stage when simulating a short circuited load with your otherwise excellent models. Don't intend to nit pick but since you're taking another look was wondering if you have any thoughts on the matter.

Edit: I see you commented since I started this post and got distracted for a while.

Pete B.

 

[andy_c]

Hi Pete,

My models have beta that's too high for Ic > 10A. I had to limit the range over which I fit beta to keep a good beta fit for normal Ic values. I'll bet that by using NK, a really good match for beta vs. Ic can be had up to the highest rated currents. I would expect that for Ic > 10A using the optimum NK, Vbe would be higher than it is now. But maybe there are other adjustments that would come into play like RB.

At any rate, I'm using FETs, so I'm not going to be looking at these devices for a while.

 

[JPV]

thermal simulation of thermaltrak transistor

Hi Pete,

My models have beta that's too high for Ic > 10A. I had to limit the range over which I fit beta to keep a good beta fit for normal Ic values. I'll bet that by using NK, a really good match for beta vs. Ic can be had up to the highest rated currents. I would expect that for Ic > 10A using the optimum NK, Vbe would be higher than it is now. But maybe there are other adjustments that would come into play like RB.

At any rate, I'm using FETs, so I'm not going to be looking at these devices for a while.

Having not yet plunged in spice, I wonder if BJT models can be very accurate in simulating thermal effects between 300 to 375 °K at low currents.

In my post 127 and following in Biasing/thermal compensation of thermaltrak transistors thread, I showed what IMHO would be a very good tracking system minimizing thermal transient induced crossover distortion.

Do you know if spice is accurate enough in simulating accuratelly these effects on distortion?

JPV

 

[AndrewT]

Andy,
you're a gem.
Thanks.

 

[andy_c]

Re: thermal simulation of thermaltrak transistor

Having not yet plunged in spice, I wonder if BJT models can be very accurate in simulating thermal effects between 300 to 375 °K at low currents.

In my post 127 and following in Biasing/thermal compensation of thermaltrak transistors thread, I showed what IMHO would be a very good tracking system minimizing thermal transient induced crossover distortion.

Do you know if spice is accurate enough in simulating accuratelly these effects on distortion?

I don't have much experience with SPICE temperature analysis. There's lots of temperature parameters for BJTs, so I assume it can do a decent job with things like DC voltage vs. temperature for things like bandgap voltage references.

But only specialized simulators and models can deal with the case in which the junction temperature varies during a transient sim due to self-heating. Gummel-Poon can't do it, but the VBIC and Mextram models support this. LTspice supports VBIC, but not varying junction temperature during a transient sim.


AndrewT: Thanks for your kind words

 

[JPV]

Re: Re: thermal simulation of thermaltrak transistor

I don't have much experience with SPICE temperature analysis. There's lots of temperature parameters for BJTs, so I assume it can do a decent job with things like DC voltage vs. temperature for things like bandgap voltage references.

But only specialized simulators and models can deal with the case in which the junction temperature varies during a transient sim due to self-heating. Gummel-Poon can't do it, but the VBIC and Mextram models support this. LTspice supports VBIC, but not varying junction temperature during a transient sim.


AndrewT: Thanks for your kind words

Thank you very much. This is to complex for a niewbie. I will go the classical way : measuring which is not always the easiest or even possible

JPV

 

[PB2]

Re: thermal simulation of thermaltrak transistor

Having not yet plunged in spice, I wonder if BJT models can be very accurate in simulating thermal effects between 300 to 375 °K at low currents.

In my post 127 and following in Biasing/thermal compensation of thermaltrak transistors thread, I showed what IMHO would be a very good tracking system minimizing thermal transient induced crossover distortion.

Do you know if spice is accurate enough in simulating accuratelly these effects on distortion?

JPV

http://www.diyaudio.com/forums/showthread.php?postid=1337815#post1337815

 

[Bob Cordell]

Plotting operating point data

I have been tweaking and making transistor models for some time now, but have not figured out how to plot simulated transistor performance parameters as a funtion of dc operating point to make model verification easy. How can I do this?

If I do a dc simulation at a desired operating point I can get most of the parameters I want from looking at the SPICE error log. If I instead do a dc sweep of the operating point, is there a way that I can plot things like ft and beta as a funtion of collector current?

I guess I would like to be able to add to the plot something like ft(q1), but that does not seem to work.

Thanks,
Bob

 

[andy_c]

Hi Bob,

To plot beta vs. Ic, you can use a circuit like below. For the plotted quantity, use Ic(Q1)/Ib(Q1). Then, to change the x-axis, left-click below it. Then you can enter the expression Ic(Q1) for the x-axis quantity.

I don't think there's any way to do this with fT. I'll post a spreadsheet that can be used for this shortly.

 

[Bob Cordell]

Hi Bob,

To plot beta vs. Ic, you can use a circuit like below. For the plotted quantity, use Ic(Q1)/Ib(Q1). Then, to change the x-axis, left-click below it. Then you can enter the expression Ic(Q1) for the x-axis quantity.

I don't think there's any way to do this with fT. I'll post a spreadsheet that can be used for this shortly.

Hi Andy,

Thanks! I guess I was being too optimistic in thinking that LTspice had a way of accessing the information in the error log for plotting. It would have been nice. I also would have liked to plot things like Ccb vs Vbc.

Cheers,
Bob

 

[andy_c]

Here is the spreadsheet that computes and fits simulated to measured fT. It's based on the equations on this page. At the moment, I have relatives visiting, so it might be best to have you look it over, then ask specific questions rather than trying to explain it all in one shot. The implementation of these formulas is in VBA, and you can see the code by pressing Alt-F11 and navigating to Module1. Roughly, these steps are done:

1) Step Vbe to get the desired Ic
2) Compute Ic at each Vbe step
3) Interpolate the measured fT to each computed Ic value above
4) Compute fT based on the device parameters and terminal voltages
5) Compute the RMS error between computed and measured fT
6) Use the solver to adjust parameters to minimize the RMS fT errror

 

[andy_c]

Oh, I just thought I'd mention about the new LTspice version available. This is a new major version, LTspiceIV.

I found a bug in the final version of LTspiceIII, in which gm for small signal analysis was computed incorrectly when the NK BJT parameter discussed earlier was different from its default value of 0.5. Transient and DC were OK. I reported this to the LTspice developer, Mike Engelhardt. He verified the bug and put in a fix. I have verified that the fix works correctly in LTspiceIV, but it looks like LTspiceIII is not going to be maintained past the last version. The final LTspiceIII does not have this fix, so I'd strongly recommend using LTspiceIV.

 

[Bob Cordell]

Here is the spreadsheet that computes and fits simulated to measured fT. It's based on the equations on this page. At the moment, I have relatives visiting, so it might be best to have you look it over, then ask specific questions rather than trying to explain it all in one shot. The implementation of these formulas is in VBA, and you can see the code by pressing Alt-F11 and navigating to Module1. Roughly, these steps are done:

1) Step Vbe to get the desired Ic
2) Compute Ic at each Vbe step
3) Interpolate the measured fT to each computed Ic value above
4) Compute fT based on the device parameters and terminal voltages
5) Compute the RMS error between computed and measured fT
6) Use the solver to adjust parameters to minimize the RMS fT errror

Thanks, Andy. I'll give it a shot.

Cheers,
Bob

 

[PHEONIX]

LTspiceIV

Hello Andy_C

LTspiceIV seems to have greater precision in THD computations is there a reason for this, or am I mistaken.

Do you know specifically what is new and better in LTspiceIV over the previous version. Is it optimised for VISTA.

Just one other thing are you a beta software tester for this software.


Regards
Arthur

 

[andy_c]

Re: LTspiceIV

Hello Andy_C

LTspiceIV seems to have greater precision in THD computations is there a reason for this, or am I mistaken.

Do you know specifically what is new and better in LTspiceIV over the previous version. Is it optimised for VISTA.

Just one other thing are you a beta software tester for this software

Hi Arthur,

I haven't actually used LTspice IV for any projects yet. I have relatives over at the moment, so the only thing I've had a chance to do with it is to verify that the bug I reported a week or so ago was fixed. I'm not a beta tester and I have no connection with Linear Technology. Anyone can report bugs in LTspice by using Help, About. Most of the UI bugs are known but I guess they are low priority, as many have persisted for years. Bugs in the simulator proper, from my one experience with this, get fixed very quickly - if you can convince the author (Mike) that it's actually a bug.

As far as what's new, here's Mike's announcement in the Yahoo LTspice users' group:

A major update for LTspice was released today. LTspice IV, formerly known as LTspice/SwitcherCAD III, features multi-threaded solvers to better utilize current multi-core processors. Also included are new SPARSE matrix solvers that deploy self-authoring code which is then assembled and linked on the fly in order to approach the theoretical flop limit of current FPU's. Large circuits run ~3 times faster on quad core processors. Small circuits will run at about the same speed as the prior version of LTspice.

Developing a parallel processing version of SPICE has been a long standing challenge in circuit simulation that has been met with limited commercial success. LTspice IV reflects a review of the techniques that have been attempted and implements proprietary methods that allow it to efficiently parallelize tasks that require as little as 5µs to run single-threaded in proportionally less time with additional processing cores.

LTspice IV requires a CPU at least as recent as the P4 and Win2K, XP, Vista, x64 variants or Linux. Support for earlier CPU's or Win95/98/ME is only through use of LTspice/SwitcherCAD III which is still available but is not expected to be further maintained.

Since that was posted, he's updated LTspice IV so it still works with older CPUs such as the Pentium III. Be sure to update to the latest.

 

[mightydub]

transistor model question

I have been playing with the ESP p3a amp in LTspice, as well as on FR4. The amp is very sensitive to breaking into oscillation with any capacitive load. Exploring this with LTspice, I noticed that the output transistors show a big glitch in their base current as they turn on/off, this appears to be what initiates the oscillation.

My question is not how to cure the oscillation, but about the base current glitch from the drivers. Is this an artifact of the model, or real, and if it is real, what is the underlying physical mechanism?

How does one address this in amplifier design, other than going class A?

LT spice waveform attached. Driver model for TIP 3055 is from OnSemi website:

.MODEL Qtip3055 npn
+IS=9.20807e-13 BF=147.096 NF=1.04318 VAF=378.469
+IKF=10 ISE=6.09693e-09 NE=2.4688 BR=14.7096
+NR=1.5 VAR=149.08 IKR=3.14824 ISC=1e-16
+NC=1 RB=14.1904 IRB=0.1 RBM=0.1
+RE=0.036413 RC=0.182065 XTB=0.1 XTI=3.71709
+EG=1.05 CJE=7.39634e-08 VJE=0.531216 MJE=0.573868
+TF=1e-08 XTF=1.35738 VTF=0.997148 ITF=0.99974
+CJC=4.44315e-10 VJC=0.400241 MJC=0.410047 XCJC=0.803124
+FC=0.653134 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1

 

[andy_c]

As promised earlier, here are some new models for the 2SA1837 and 2SC4793 driver BJTs. These use the NK parameter to get the best possible fit of beta vs. Ic at high currents. I've fit beta vs. Ic, fT vs. Ic and ln(Ic) vs. Vbe as closely as possible to the datasheets. Other parameters such as forward and reverse Early voltages were obtained from on old DOS version of the SpiceMod program I have lying around.

All standard disclaimers apply - void where prohibited, cannot take responsibility for bogus simulation results, etc.

 

[andy_c]

Oops - I had the 2SA1837 as an NPN because my SPICE test jigs are all NPN. Sorry about that error folks. LOL! Here's the corrected one. Please ignore the previous file.