I propose for discussion a new project SRC on dual AK4137. The first AK4137 upsumpling PCM to 176/192, the second converts to DSD256.
Dual AK4137 allows you to convert to DSD256 without significant loss in quality.
This cape cannot claim to be HQPlayer's conversion quality, but it can compete with Roon software conversion.
The firmware for the BeagleBone will be published later. After I debug her work.
The project is open. I will be happy to hear your wishes for further development.
P.S.
I updated the DSD'it versions. A complete set of documentation always available at http:://puredsd.ru
Dual AK4137 allows you to convert to DSD256 without significant loss in quality.
This cape cannot claim to be HQPlayer's conversion quality, but it can compete with Roon software conversion.
The firmware for the BeagleBone will be published later. After I debug her work.
The project is open. I will be happy to hear your wishes for further development.
P.S.
I updated the DSD'it versions. A complete set of documentation always available at http:://puredsd.ru
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Hi ppy
probably would be better to add +1 flip flpo at the recklocking output.
- avoided metastability
- using one double Flip-Flop standard package per line will decrease intermodulation between lines.
- separate decoupling of FF ic will decrease ground bounce and improve signal integrity
- in case of cascaded Flip flop recklocking You wil have exact one MCK delay of all sygnals, when in case of one F-F used delay is 1/2 of MCK and there is the difference in terms of rising edges strat then in the input...
...
Another thing is designig for signal integrity that is sort of simple: between every IC interconnection put one R and trim each value to eliminate ringing at the edges. That will tremendously decreased noise coming from ground bouces when sygnal at the edges are higher then power suply value...
...
In that direction simple shunt regulator for each IC or segment of ICs are helping more.
Because of closing current consumption loops slose to the power pins of ICs.
...
These few things have huge impact to th final sound result i tried it.
cheers
probably would be better to add +1 flip flpo at the recklocking output.
- avoided metastability
- using one double Flip-Flop standard package per line will decrease intermodulation between lines.
- separate decoupling of FF ic will decrease ground bounce and improve signal integrity
- in case of cascaded Flip flop recklocking You wil have exact one MCK delay of all sygnals, when in case of one F-F used delay is 1/2 of MCK and there is the difference in terms of rising edges strat then in the input...
...
Another thing is designig for signal integrity that is sort of simple: between every IC interconnection put one R and trim each value to eliminate ringing at the edges. That will tremendously decreased noise coming from ground bouces when sygnal at the edges are higher then power suply value...
...
In that direction simple shunt regulator for each IC or segment of ICs are helping more.
Because of closing current consumption loops slose to the power pins of ICs.
...
These few things have huge impact to th final sound result i tried it.
cheers
Thanks Zoran!
P.S. My English is very bad. Maybe I misunderstood you.
PPY's recklocer similarly designed and stable. But if I see with an oscilloscope that the AK4137 signal falls into the metastability zone, then I will definitely correct the problem. But can it be more convenient to do this not by adding three flip-flops, but by shifting the MCLK signal by 3-4ns through one Schmitt trigger? The 74AUP2G79 has a metastability window of only 1ns.
Double Flip-Flop does not allow placing on the PCB as close as possible to the Amanero standard output connector.
Yes, I will do it in the second version. I have already ordered PCB fabrication.
Between every IC interconnection 3-7mm. At these distances, there are no reflections that the series resistor can correct.
P.S. My English is very bad. Maybe I misunderstood you.
Something based around TL431. Dependinon consumption of IC. But if the IC consumption at high operating F lets say "larger" use transistor. It is very basic and simple scircuit from datasheet of tl431. I gues that needed V is 3.3V for the supplys?
for instance max IC consumption is 10mA + (120% of 10mA) = 32mA total
Yes it deserves more pover from central PSU regulator, and produces a slight more heat on the pas Resistor (or Transistor) and also a bit more heat at the shunt element. But it is worth. And not so waste on the PCB...
Also theese signal integrity R on the each signal path between the ICs deserves some more time to trim and replace.
You can try it on some other circuit it is clear on the scpe and You will also notice improvement in sound. That huge ground bouces simple could not be cut out with filters without impact on phase and sound in general. So this is the method to minimize them at the source?
Hi ppy i have take a look at the sch You linked.
The goal is to keep separate I2S lines all of the transition lines.
Not to merge all I2S lines into single IC. and multiple times.
The lines are from different frequency and for my opp should not be interfered in the small space die-s in ICs...
I have good results with single digital isolator ADuM1100
I think that You don't need buffer from the amanero outputs?
You can go direct to the isolators. BUT if You want enable function before isolators You can use single high speed buffer with enable function for EACH I2S line. That is much simply-er internal structure circuit.
...
Actually ou did some signal integrity treatmant with Resistors anthe linked sch, but only in one interconnection place. Should be between each IC. And walue of 33ohms is small and insufficiant. That should be checked by the measurements with osciloscope and trimer pot at each point. From my measurements these the values are higher round to 100ohms.And it depends of frequency. Simply, You dont nedd the spikes beyound the pover voltage upply at EACH 1/2 sygnal,
and with all of ICs used. Anyway the logic levels are smaller than powr supply value and we dont nedd at all that multiplied, constant glitch energy in the device.
That comes from the tipicaly powerful drivers that drives low capacitance inputs of the next gates, mainly. These outputs are designed to drive about 15 gates, and in most digital audio devices they drive just a single gate... So it is not mainly about reflections.
...
The issue abot flip flop. When You clock some data in the flip flop then the data will be at the output "delayed" by the 1/2 of in our case MCK. So the MCK in relation with all lines will be at the oposite rising/falling edge of the signals we recklock. When You add just one F-F after first one in series, clocked with same MCK, the signals will be "delayed" by the full one cycle of MCK and all of the lines will be in the same rising.falling edges LIKE it was in the input of the recklocker.
You cant measure positively meta-stability with conventional equipment I think?
No need for that because in every scholar literature stated that it was measured and the recommendation is to serialize the F-F.
.
Off course for max sampling rate input frequency You need minimum 2 times higher F for MCK. For instance at the 384KHz SR BCK is high F and Yu need 47.xxxMHz MCK to achieve recklocking. For up to 192KHz SR 27.xxxMHz is minimum.
...
Dont get me wrong about suggestions, I like Your work and just want to share my expiriene and informations
cheers
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Hi Zoran,
May I ask what scope probe you use for those measurements?
Also, my understanding is that using 100-ohm series resistor will help clean up I2S signal a little more as seen on a scope, but at the expense of slower rise time. Any comments on that?
Hi I use not so expensive probe at the 100MHz range. The more accurate equipment will perform naturaly better. Probe should be calibrated as standard step with internal trim C,and some square generator signal usualy already present at the scope.
If You "cutout" the glitches, and square signal, I thik tha You cant loose "speed", because logic "1" is usually beyound the uuper line of the sygnal, and logic "0" is slight more than ground. These datas about logic levels, are almost always presented in the datasheet for the specfic part. The goal is to keep the signal within the lets say power supply range from top and from the ground side too, without ground bounces.
...
Value of the resistor depending on driver, next logic gate and frequency mainly. And can be different in different casses. Because of that I said that it should be trimmed for specific PCB, power supply and set of IC used on pcb. I mean it is not that huge job of spend some hour more? I am aware that almost nobody does that and if is tha case that is "classic" 22ohms or 33ohms, without checking it with measurements...
If You "cutout" the glitches, and square signal, I thik tha You cant loose "speed", because logic "1" is usually beyound the uuper line of the sygnal, and logic "0" is slight more than ground. These datas about logic levels, are almost always presented in the datasheet for the specfic part. The goal is to keep the signal within the lets say power supply range from top and from the ground side too, without ground bounces.
...
Value of the resistor depending on driver, next logic gate and frequency mainly. And can be different in different casses. Because of that I said that it should be trimmed for specific PCB, power supply and set of IC used on pcb. I mean it is not that huge job of spend some hour more? I am aware that almost nobody does that and if is tha case that is "classic" 22ohms or 33ohms, without checking it with measurements...
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Thanks to Zoran for the advice. I will try to take your advice. But I would like to keep the balance between device cost and efficiency. This reclocker should be several times cheaper than the cost of HQPlayer. I consider HQP to be the benchmark for sound quality. And if this device will approach the cost of HQP, then apparently there is no point in developing it.
A separate shunt regulator for each chip seems redundant. The device from the topic will be assembled to debug the software and evaluate the effectiveness of such a solution. If the result is good, then your advice will also help me a lot. I don't consider myself a good circuit engineer. Therefore, I am ready to learn.
By the way, metastability is measured quite well by an oscilloscope - https://www.siue.edu/~gengel/GALSproject/MeasuringMetastability.pdf
A separate shunt regulator for each chip seems redundant. The device from the topic will be assembled to debug the software and evaluate the effectiveness of such a solution. If the result is good, then your advice will also help me a lot. I don't consider myself a good circuit engineer. Therefore, I am ready to learn.
By the way, metastability is measured quite well by an oscilloscope - https://www.siue.edu/~gengel/GALSproject/MeasuringMetastability.pdf
Hi Pavel. Nice to see you again.
I'll try to explain my idea. My resident source for DSC2.5.2 dac is a passive Pc (as yours) with OSX OS and HQPlayer that see BeagleBoneBlack as a NAA. This is an high quality solution but can't be used for Internet Radio playout.
As an alternative Digital Source I would like to connect a Streamer to my DSC2.5.2 ... Unfortunately most of the Streamers can't provide PCM to DSD conversion (2K EUR Lumin M1 does), so I can't connect a low cost streamer to DSC2.5.2
Can I use your new projct in combination to a Streamer and DSC2.5.2 in order to convert PCM flow coming from the streamer and send it to DSC2.5.2?
I have a couple ideas and, if you don't mind, I like to post here for discussion. I think many are using a BBB before and a DSD Dac after. Mostly, we will be playing DSD source, and for the rare occasion that we play PCM and are too lazy to convert format ahead, we can use the AK for help.
[1] Add a U.FL connector for each oscillator, for those who wish to use external clocks.
[2] Add buffers before the AK, and if DSD is selected, route the signal directly to the reclocking flip-flops and bypass the AK all together.
[3] Allow external power supplies.
[1] Add a U.FL connector for each oscillator, for those who wish to use external clocks.
[2] Add buffers before the AK, and if DSD is selected, route the signal directly to the reclocking flip-flops and bypass the AK all together.
[3] Allow external power supplies.
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- Don't understand how you want to use external clocks. I don't really like this idea. The connection diagram and switching of frequency domains 44/48 are becoming more complicated. I plan to install fairly high-quality clocks NDK NZ2520SDA and the tracing of critical high-frequency lines on the PCB does not exceed 4mm.
- This has already been implemented on the 74LVC157 multiplexer
- No problems! In the final version, I will provide an external power connector.
1. I guess the reason wanting external clocks is "why not" I do want to try the well tempered clocks
The Well Tempered Master Clock - Group buy
Reading the NDK datasheet, it has a "stand-by" mode. So, it is a clock and a clock buffer with enable. The two clocks (only one is active at any time) are connected to a clock fan-out buffer U4. If we replace U4 with a 2:x clock buffer/driver with input mux such as
https://www.silabs.com/documents/public/data-sheets/si5330x-datasheet.pdf
then the two clocks can be active at all time. CLK_SEL will connect to the clock fan-out buffer directly.
Those who like to use external clocks can just not soldered everything before the oscillators - U2, U1, L1, C1, C2, X1, U5, L2, C3, C4, and X2.
2. Thanks. I see it now. May I ask another question: on your PPY's ReClocker, you use SI digital isolators and here you omit them. Do you find them to be not effective?
3. Thanks again.
The Well Tempered Master Clock - Group buy
Reading the NDK datasheet, it has a "stand-by" mode. So, it is a clock and a clock buffer with enable. The two clocks (only one is active at any time) are connected to a clock fan-out buffer U4. If we replace U4 with a 2:x clock buffer/driver with input mux such as
https://www.silabs.com/documents/public/data-sheets/si5330x-datasheet.pdf
then the two clocks can be active at all time. CLK_SEL will connect to the clock fan-out buffer directly.
Those who like to use external clocks can just not soldered everything before the oscillators - U2, U1, L1, C1, C2, X1, U5, L2, C3, C4, and X2.
2. Thanks. I see it now. May I ask another question: on your PPY's ReClocker, you use SI digital isolators and here you omit them. Do you find them to be not effective?
3. Thanks again.
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Thanks for developing this new project Pavel.
Although I'm following this thread I've not really looked at it in detail yet but this looks really interesting; would it be reasonable to think of this as a version/development of your isolator/reclocker (for example in the use case of streaming DSD from HQPlayer with the BBB as an NAA) but with the option of upstream AK4137-based SRC when its required - the best of both worlds - or am I missng something?
I guess that, when you're ready for it to hit the street, you'll offer your usual downloads of gerbers and firmware so assembly will be down to the builder.
Although I'm following this thread I've not really looked at it in detail yet but this looks really interesting; would it be reasonable to think of this as a version/development of your isolator/reclocker (for example in the use case of streaming DSD from HQPlayer with the BBB as an NAA) but with the option of upstream AK4137-based SRC when its required - the best of both worlds - or am I missng something?
I guess that, when you're ready for it to hit the street, you'll offer your usual downloads of gerbers and firmware so assembly will be down to the builder.
