Valve DAC from Linear Audio volume 13

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#44
randytsuch said:
Slave mode would be fine, but would probably want "option 2", with support for different word to bit clock ratios.

At least this isn't the really complicated option lol
Click to expand...

I've had a look at the Verilog code of the prefilter.v module that interfaces with the DIX4192 (see the attachments, I've renamed it to prefilter.txt because the forum doesn't allow .v). I wrote it more than a year ago, so it took me a while before I fully understood my own design again.

There are actually two things that need changing to support bit-clock-to-word-clock ratios different from 64. One is changing the code such that the incoming bits end up at the right place independent of the ratio of the bit clock to the word clock.

The other is generating the clocks that come out of prefilter.v (and go into the SRC4392) in a different way. Right now I derive them from the incoming bit clock, but I have to change that to the incoming word clock. This is a bit more complicated, especially since the frequency of the incoming word clock is too low for the Spartan 6 PLLs and the jitter can be too high for the Spartan 6 DCMs. I think I'll make a frequency-locked loop with a rate multiplier as numerically controlled oscillator.

Anyway, I'm looking into this, but it will take a while before I got it debugged and running.

Are there any specific signal sources and bit clock to word clock ratios you are interested in?
 

Attachments

#45
Hi all,

Well, I just programmed my new configuration file into an FPGA board to see if it works. I haven't had a chance to test any of the new functions yet, but at least it is still functional: it is playing David Bowie's last CD right now.

If everything works as intended, these functions are added (with thanks to Randy for the discussion we had over PM about what functions would be useful):

I2S interface on the extension connector that can handle anything from 8 to 32 bits with a bit clock of 16 to 64 times the word clock, with de-emphasis and mute inputs and with support for DSD64 via DoP

Input that changes the I2S interface into a raw DSD interface

Support for DSD64 and DSD128 over the raw DSD interface

Merry Christmas everyone!
 
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#48
The raw DSD64 and DSD128 interface also works now. I connected a simple analogue sigma-delta modulator to it and played some dance-hall reggae through the chain.

The day before yesterday it didn't work at all due to a silly bug; I had specified three-bit patterns as 010 and 011 instead of 3'b010 and 3'b011, which means they were interpreted as decimal 10 and 11. As a three-bit pattern can never be ten or eleven, the Xilinx programs recognized it as redundant logic and optimized out a part of the design (-;
 
#51
I think your design choices and specs are very sound. I wish there was a design not using toobs as it brings so many special aspects. Can you do a version replacing the tubes with it's solid state siblings - "everything else equal"? Maybe except for the clocking solution - how about an USB interface working in a mode as slave to the I2S i/f, absorbing any clock differences - then one single clock stiff operated to the conversion engine could be used - re-clocking on the backside of the FPGA!!

//

MarcelvdG said:
There are four inputs. Three of them are either AES3 or SPDIF inputs, depending on how you connect them and what termination resistors you put on the board. The fourth is meant to be connected to a Toslink receiver, either one working on 3.3 V or on 5 V. If you need more Toslink inputs and you can obtain 3.3 V Toslink receivers, you can easily convert some of the other inputs into Toslink inputs.

The inputs accept word lengths up to and including 24 bits and sample rates up to and including 192 kHz. DSD64 via DoP is also supported.

There is no USB or I2S input, but all required hardware is available, so if you are prepared to rewrite the FPGA code, you can add them yourself. The FPGA board is a TE0630 micromodule from Trenz Electronic with an XC6SLX75-3CSG484I FPGA, see Mikromodul Spartan-6 XC6SLX75-3CSG484I Industrial Temp. Range | Trenz Electronic Online Shop (EN)

If you are looking for a DAC with spectacular dynamic range numbers, my valve DAC is not what you are looking for. It is a DAC that has all analogue and mixed-signal processing done by valves. To keep the number of valves down to a reasonable number, this means that the actual DAC circuit is relatively simple, which results in relatively modest dynamic range numbers; I measured 85.76 dB(A) on the left and 91.29 dB(A) on the right channel. Nonetheless, I've never heard its noise during normal use, neither over loudspeakers nor over headphones. The harmonic distortion is about 0.016 %.

I measured the frequency response to be flat to within +0 dB/-0.21 dB between 20 Hz and 20 kHz. I don't know how much of this roll-off is actually due to the measuring equipment. By design the -3 dB point should be 82 kHz (for high sample rate PCM).

The digital filter chain has very low ripples to keep pre-echoes down. The worst digital filter is the one in the SRC4392 asynchronous sample rate converter with its +/- 0.007 dB ripple, everything else is in the +/- a few millionth of a dB ballpark.

The DAC has an apodizing filter that can be turned on or off. There is also a surprise mode for blind testing, so you can check what sounds best without having to worry about expectation bias.

Unusual features of the digital signal processing part are the fact that there is adequate headroom for filter overshoots and that the anti-imaging filter is actually designed to prevent imaging - unlike most commercial digital filters, which have no (documented) headroom and hardly suppress imaging at all between 0.5 fs and 0.55 fs.

Jitter of the incoming signal is strongly suppressed by the SRC4392, so it can work well with sources of which the clock is not very clean.
Click to expand...
 
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#53
Resurrecting this thread as I might be interested in having a go at a Native DSD-only derivative - I saw on the Group Buy thread that this is possible. Can you say a little about what that involves please Marcel.? I'm an experienced assembler but I struggle with the theoretical side so please be gentle.


I am currentlly just finishing a Signalyst based DSD decoder using boards from DIY Audio user ppy. My plan would be to feed the Valve DAC from a Beaglebone black, via a reclocker/isolator. This would output a DSD data stream folowing 44.1 an 48KHz rate multiples, which I would prefer to retain rather than using any sample rate conversion.
 
#54
A raw DSD version would boil down to just building the actual DAC, reconstruction filter and voltage reference. The digital part would become just a few flip-flops and the crystal oscillator would have to be replaced with some circuit that can buffer an external clock.

Would your set-up have an external master clock signal available and if so, is there any information available about the timing relation with the raw DSD bit clock?
 
#55
Probably the simplest solution would be to use CMOS logic gates to level translate and buffer/invert the external clock and then capacitively couple it into the bottom E88CC of each channel. The ECC81 and two EF80s would then not be needed anymore. That would reduce the number of valves to seven: three E88CCs per channel and a common 85A2 reference.

Is there any information on your reclocker/isolator?
 
#56
Thank you Marcel.

I would most likely use a Twisted Pear Audio (TPA) Cronus as the 'source';

Cronus Reclocking

The Cronus has outputs for the raw DSD data streams, the DSD Clock and Master Clock. The Master Clock oscillators on the Cronus are switched automatically to align with 44.1/88.2/176.4/etc or 48/96/192/etc data families (for my current project I use 45MHz and 49Mhz oscilators but 22/24MHz can be used). In essence the Cronus outputs are ready for the decoder.

For information, upstream of the Cronus I use Signalyst HQPlayer, resampling FLAC files (mostly 44.1KHz rips but some 48KHz family files) to DSD (upto DSD512 - 22MHz), streaming the data over the network to a Beaglebone Black (running a DSD specific linux distro) and thence via a TPA Hermes isolator to the Cronus reclocker.

The set-up also has signals for DSD on/off and Mute - on his boards ppy uses these to suppress thumps when there are DSD data rate changes and the like so it would be good if this functionality were to be replicated.
 
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#57
MarcelvdG said:
Probably the simplest solution would be to use CMOS logic gates to level translate and buffer/invert the external clock and then capacitively couple it into the bottom E88CC of each channel. The ECC81 and two EF80s would then not be needed anymore. That would reduce the number of valves to seven: three E88CCs per channel and a common 85A2 reference.

Is there any information on your reclocker/isolator?
Click to expand...


It would appear that a new PCB would be the way to go - much more compact if all the unnecesary stuff is removed so lower cost and easier to house, plus no FPGA board to be purchased.

Maybe integrate the output filters onto a single board?
 
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#58
Pavel (DIYAudio user ppy) has a couple of DSD projects available for DIYers on his website;

https://puredsd.ru/

One of the projects integrates isolation/reclocking, similar to Hermes/Cronus, with the Beaglebone Black (or Amanero USB board) plugging onto the decoder board. Now, if it were possible to 'cut and paste' that part of ppy's board onto the front end of a DSD specific version of your board...
 
#59
Hi Marcel, any thoughts on the Cronus interfacing with your board?

I'm not overly technical but I've started to work through your Linear Audio paper and to explore the contents of the download, in particular the schematics.

I see the download includes some KiCAD files. I presume this means I could edit these files to create a DSD only version and generate new gerber files? I haven't used KiCAD but have done some simple PCB design before and have a friend who is familiar with KiCAD so I'm thinking I ought to be able to edit the PCB design. If I start with removing the sections that wouldn't be needed first I'll have time to investigate what's needed to interface it to the Cronus.

Conceptually I need to get my head around the clocking aspects as I'm not sure what clock signal (DSD bitclock and Masterclock) is relevant where.

BTW, have you tested your DAC with raw DSD input? I'm assuming, at least for now, that eliminating the FPGA/resampling/clocking elements of your design opens the way to using high data rate DSD streams, such as DSD256 and DSD512?

Sorry if this is a bit scatter gun at the moment but I'm still working with a fairly basic understanding.
 
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#60
Actually that's what I am trying to do: first see how to make a simple raw DSD interface for a DSD-only variant (there are some timing issues I'm looking into) and then update the KiCAD files. I have no intention of actually building it, as I already have a valve DAC, I just want to supply you with a paper design and layout that are likely to work.

In the original valve DAC, the sigma-delta modulator in the FPGA runs at 27 Mbit/s, so in DSD terms that is equivalent to DSD612+12/49. Hence, the DAC should also be functional at DSD512.

About the reclocking: I tried to look up puredsd.ru several times this evening and only got error messages. It's a pity because I never understood how reclocking is supposed to work. Do you simply have two asynchronous clocks with nominally equal frequency and take for granted that due to frequency tolerances, every now and then a sample gets repeated or skipped? If so, why would that be better than just having a bit more jitter? Or is there some synchronization mechanism involved, or just a very long FIFO that is filled up half before you start to listen? (The Twisted Pear website does work, but it has schematics and manuals of almost everything except the Cronus reclocker.)
 
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