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Signalyst DSC1
Signalyst DSC1
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Old 22nd October 2015, 02:54 AM   #151
jborden is offline jborden  United States
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Quote:
Originally Posted by jps1964 View Post
here the different schematics:
- 8-bit tap (8x 15k),
- discrete I/V-converter (500R; +2.5V bias --> thanks Patrick),
- and the two Sallen-Key filter (94kHz and 166kHz).

Do I forget something, I mean principally, coupling capacitors? Open for sinnfull modifications...

Jean-Paul
I very much like the approach. For the Sallen Key filters, I am inclined to go with a B1 buffer as the basis -- not too different from what you have, really very close. I am suggesting this because this already exists, essentially but with diifferent values, as the B-4 active crossover.

Now interestingly, both of these can readily be made balanced as the SEN, so from the point of view of what DSC2 might look like, and assuming we use this approach for the discrete IV and filters, what would the digital input look like? ... would it be as simple as placing an inverter on the DSD input line?
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Old 25th October 2015, 12:21 PM   #152
jps1964 is offline jps1964  Germany
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Hello,

I reiterate my question about coupling between the different stages to know if I can go completly DC and only place a coupling cap at the output of the last Sallen-Key filter?

Ive asking Patrick (EUVL) for helping to built a last version of his simplistic OPAMP to use as output buffer.

JLSOUNDS give me 3D datas for the I2SOVERUSB converter: Im working on some missing components but the results are today quiet good, please see the attachment...

Jean-Paul
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File Type: jpg DSC1_NEU_COMPLETE_SKETCHUP_3.jpg (350.8 KB, 674 views)
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Old 31st October 2015, 04:52 PM   #153
jborden is offline jborden  United States
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Default ARM/FPGA SFP optical input, I2S output NAA

I've been looking at SFP input and I2S output with networkaudiod running on a low powered CPU. sm31 pointed this out: Optical Network Configurations - Page 16

This product will use the Xilinx 7010/7020: krtkl

So a driver would need to be written/modified to get I2S output on the pins ... doable?

I am thinking this would be a terrific platform to create a direct Ethernet input for the "DSC2".
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Old 6th November 2015, 03:48 AM   #154
jborden is offline jborden  United States
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Default Inverter for Balanced?

Does anyone know? Would placing an inverter on the DSDR and DSDL lines provide the input to a balanced DSC1?
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Old 6th November 2015, 06:07 AM   #155
jps1964 is offline jps1964  Germany
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... D flip-Flop... see no DAC thread...
Jean-Paul
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Old 10th November 2015, 05:54 AM   #156
jborden is offline jborden  United States
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Default Balanced DSC

So balanced DSC is as easy as:
DSC1b.pdf

And then dual I-V Sen and filters.
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Old 10th November 2015, 06:08 AM   #157
jps1964 is offline jps1964  Germany
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I know but more complex then only transformer LPF.

Jean-Paul
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Old 10th November 2015, 01:22 PM   #158
jborden is offline jborden  United States
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Not just transformer I'm thinking relays to switch between discrete SK filter eg B1 buffer based vs. M2 "enhanced" transformer -- the M2 sounds so good in real life that it might be a good option, but it would be good to be able to test side by side


Sent from my iPhone using Tapatalk
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Old 13th November 2015, 02:50 AM   #159
jborden is offline jborden  United States
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Default Balanced DSC

Schematic for a Balanced DSC shift register and resistor ladder module:
Balanced-DSC.jpg
and board:
BalancedDSCboard.png
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Old 16th November 2015, 05:36 AM   #160
jborden is offline jborden  United States
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Default Balanced DSC

Perhaps I'm being too compulsive, but I've re-layout the board so that the BCLK has a constant path length to the shift register chips:
Bal.DSC.png

In this case the clock and DSD signals come in via U.FL. This board is for each channel.
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