john curl said:
Yes, the DCFQ circuit solves a lot of problems with only four transistors. When I built it I used NPD5564's, but they are no longer available, so I simm'd it with the LSK389 parts. Stable as a rock and flat to beyond 10 MHz. Just remember where you saw this circuit first 🙂.
Cheers,
Bob
Bob Cordell said:
Since the subsequent input J1-J2 is now buffered by the DCFQ, is there any advantage to using the LSK389 JFETS for the subsequent input other than lower current noise (and perhaps lower first stage transconductance for higher slew rate)? Perhaps a subsequent input with low-noise bipolar transistors and reducing R5,R10 for lower inverting input source impedance can provide similar noise performance.
nuvistor said:
You make a very good point, but I would tend to keep the JFET input stage. Here's why. The first reason would be that one really does not want to reduce R5 & R10 any lower than they already are, since that will further load the DCFQ and increase its distortion.
Second, the DCFQ is a very fast stage, so it doesn't really do much to buffer the input stage from things like RF from the outside world. In simulation the thing was flat to about 40 MHz. Of course, in a real application, one would have some passive RFI LPF in front anyway, with or without the DCFQ. Also, for those concerned about RFI ingress back to the input stage from the output via the feedback path, the DCFQ does nothing to mitigate this.
So I guess where I'm coming down is that most of the reasons that one would have used a JFET stage in the first place are largely still there with the DCFQ in the circuit. Of course, those who prefer bipolar input differential stages would also be able to make a good design. In their case, however, they might be more inclined to use a bipolar arrangement in place of the DCFQ.
Cheers,
Bob
Bob, I must say the the inclusion of R37 is unique. I would not have thought of that. The rest is pretty much what we do already, except that I don't like to add active devices. By your count, I have only added one fet, and no bipolars in my JC-1 design.
I would add, one more fet, and no bipolars in a revised design.
By MY count, I would have to add one more matched fet pair to the input. I can reach roughly equal noise, since I start lower with my basic topology.
What do you mean that you can't get 5564's? I have hundreds of them, maybe you and others might want to buy some, in future. I am only offering a service here, they can sit here forever, for all that I care
I would add, one more fet, and no bipolars in a revised design.
By MY count, I would have to add one more matched fet pair to the input. I can reach roughly equal noise, since I start lower with my basic topology.
What do you mean that you can't get 5564's? I have hundreds of them, maybe you and others might want to buy some, in future. I am only offering a service here, they can sit here forever, for all that I care
Thanks for the gracious and detailed reply.
I expect low-noise low-offset dual JFETs to be preferred by those with a ready supply of them, but since the decline of analog sources like phono and tape and improvements in FET-input opamps they have become harder to come by for the average DIYer. A limited selection of fairly well offset-matched dual BJTs in SMD packages (SOT23-6) are now available from Digikey and Mouser, and a fair yield of matched pairs can be had from a lot of 100 discrete BJTs; similar matching for discrete JFETs has lower yield due to the much greater distribution of Vgs vs. Vbe.
I suspect a bipolar DCFQ with the same bandwidth as the JFET one would be more prone to minor-loop oscillation due to the higher transconductance of BJTs. Reducing the input pair current would solve this but reduce bandwidth.
Perhaps the LTSpice .asc file could be posted for those interested in evaluating this design?
I expect low-noise low-offset dual JFETs to be preferred by those with a ready supply of them, but since the decline of analog sources like phono and tape and improvements in FET-input opamps they have become harder to come by for the average DIYer. A limited selection of fairly well offset-matched dual BJTs in SMD packages (SOT23-6) are now available from Digikey and Mouser, and a fair yield of matched pairs can be had from a lot of 100 discrete BJTs; similar matching for discrete JFETs has lower yield due to the much greater distribution of Vgs vs. Vbe.
I suspect a bipolar DCFQ with the same bandwidth as the JFET one would be more prone to minor-loop oscillation due to the higher transconductance of BJTs. Reducing the input pair current would solve this but reduce bandwidth.
Perhaps the LTSpice .asc file could be posted for those interested in evaluating this design?
john curl said:
Hi John,
It sounds like what you do already is just a single FET buffer on the negative input side, with no help from a CFP. I would imagine that would give you some significant second harmonic distortion, and that its effect would not be the same for all three operating modes.
I guess I'm not surprized that you object to my use of bipolars in the CFP, which of course means local feedback. If I understand correctly, not counting current sources, you use one JFET in the JC-1 and I use two JFETs and two bipolars. So if counting devices matters, you're right, you have fewer. Even Charles Hansen doesn't count devices anymore as a measure of audio purity.
I do not believe that your basic topology is even as low noise as mine, given the noise numbers you are achieving. You are not even close to 7 nV/rt Hz. I honestly don't know why your amplifier is not quieter than it is; maybe you are getting a lot of input-referred noise from the noisy MOSFETs you use.
The National Site does not even carry the spec sheet of the NPD5564 any more. That's why I thought they were no longer available. They were a great part. Didn't you like them?
Is the identical part made by someone else today?
Cheers,
Bob
Bob, a complementary differential fet input stage made of a Toshiba 2SK389 and a Toshiba 2SJ109, operating at 2 ma per device, and no 100 ohm degeneration resistors is QUIETER than your input stage. All else being equal.
5564's are no match to 109's. I have used them for 35 years.
5564's are no match to 109's. I have used them for 35 years.
john curl said:
Hi John,
Since the best outcome of our discussions (disagreements?) is that the readers and particpants in the thread actually learn something, why don't you explain why you believe that the complementary differential FET input stage is quieter than mine, all else being equal. This is a lot more educational than you just saying it is so, don't you agree?
Since we are comparing basic architectures here, rather than personal choices of which JFET to use or whether to use degeneration, let's pit my architecture using 2SK389 with no degeneration, against the complementary architecture using 2SK389 and 2SJ109. Explain the principle behind why you assert that the complementary architecture is quieter.
Cheers,
Bob
What input topology is best when no global feedback is used?
Unipolar? Complementary? Wierd Science?
Would comparing upper order harmonic distortion be the best test?
Unipolar? Complementary? Wierd Science?
Would comparing upper order harmonic distortion be the best test?
Because 2 devices are in parallel, and 2 devices are in series.
Your design only has 2 devices in series. Also, remember the 2n5564 is your chosen fet pair. It has lower Gm and higher 1/f than the 2sk109.
Your design only has 2 devices in series. Also, remember the 2n5564 is your chosen fet pair. It has lower Gm and higher 1/f than the 2sk109.
I should have said 2SJ109, or 2SK389. I don't want to confuse anyone more that they already are. 😉
Bob, I looked at your circuit and wonder if the total noise contribution from the newly added front end buffer is lower than going for a direct differential approach into the original fet inputs. To suit the average pre-amp, the value of R6 would probably have to go to 10k Ohms, and R10 by a similar amount on the inverting input side.
BTW, my assumption is that the pre-amp should be able to drive circa 10k load without too much difficulty.
One other thought, to increase the input impedance of the - input, there may be some bootstrapping tricks that could be used.
BTW, my assumption is that the pre-amp should be able to drive circa 10k load without too much difficulty.
One other thought, to increase the input impedance of the - input, there may be some bootstrapping tricks that could be used.
john curl said:
Hi John,
This answer doesn’t appear to reflect your status as a noise expert. I’m sure Bob Pease would grumble and give it a failing grade.
All you are saying here is that the complementary differential architecture effectively puts two input stages in parallel. The signals from the N-channel pair and the P-channel pair are correlated and add on a voltage basis in the VAS (+ 6 dB). The noise from the N and P pairs is uncorrelated and adds on a power basis (+3 dB). So we end up ahead of the game by 3 dB by having a second input pair. Most of us learned this on the second day of Noise 101.
If that was all there was to the story, your answer would be right (and complete). If that was all there was to the story, your amplifier would have an input referred noise close to the 1.2 nV/rt Hz on the spec sheet of the 2SK389 at 2 mA. Using a diff pair increases the noise 3 dB compared to the single-ended (spec sheet) value, and paralleling two stages drops it back down 3 dB, so you wind up at the spec sheet value. Its not all there is to the story. Would that our amplifiers were this quiet.
John, it’s not just the intrinsic noise contributions of the input devices. Your simple answer implicitly assumes that it is.
Besides the resistances in the circuits, the main thing you have completely ignored here is the input-referred noise contribution of the VAS. That contribution is a lot bigger in your architecture due to the fundamentally smaller gain of the first stage (as compared to my unipolar architecture).
If you really believe that the complementary architecture is fundamentally quieter in any but the most simple-minded academic case, you need to work harder at arguing the point, calling on more of your Noise Expert abilities.
Cheers,
Bob
Bob, you are going to confuse the issue. First, I have a 2200 ohm load resistor. That gives me a fairly high voltage gain. You are probably correct that the linear noise response is slightly effected, but I am most concerned about the A weighted response, and the fets get quieter at higher frequencies.
Actually, I think that most of the MIDRANGE noise is generated by the extra 10K that I have as series resistance in my circuit. Why don't you do a noise analysis of my input stage (as much as you know already should work) and then we can compare notes.
Actually, I think that most of the MIDRANGE noise is generated by the extra 10K that I have as series resistance in my circuit. Why don't you do a noise analysis of my input stage (as much as you know already should work) and then we can compare notes.
john curl said:
I'm trying really hard not to confuse the issue, and I hope I'm not.
If you have a 2.2K load and are running 2 mA, I guess the resulting 4V or so is the forward gate-source bias on your MOSFET VAS transistor, right?
What MOSFET device are you using in the VAS and what bias current are you running it at?
The challenge here is in properly incorporating and modeling the input noise of the MOSFET. My impression is that they are pretty noisy, but I've never measured one for noise because I have not used them in small signal applications. Have you ever measured the input-referred noise of one of these MOSFETs? If not, can you do the measurement? I'm not sure whether I can trust the noise modelling for the MOSFETs in the usual MOSFET SPICE models.
Thanks,
Bob
Small MOSFETs on the input offer a rather substantial increase in gm over JFETs, and because they are enhancement mode, there is a lot more leeway with chosing the current, and therefore, potential for even more gm.
@Bob C, your concerns about noise are well founded. In general MOSFET models do not even offer any useful noise modeling as they are normally not intended for applications that require it. That being said, I do have some experience with MOSFET inputs and yes, they are substantially noisyer than bipolars and JFET inputs, the advantage being no noise current, so if your amp is fed from a high impedance source (like a volume pot!) there is some advantage over bipolars, but not over JFETs. Voltage noise-wise, they are the worst of the three, at least types i have used, but in a power amp, IMHO their other virtues outweigh the shortcomings. Unfortunately I am not in a position right now to offer measurements, other than the 'ear to tweeter' type, at the moment, so take this for what it's worth.
@Bob C, your concerns about noise are well founded. In general MOSFET models do not even offer any useful noise modeling as they are normally not intended for applications that require it. That being said, I do have some experience with MOSFET inputs and yes, they are substantially noisyer than bipolars and JFET inputs, the advantage being no noise current, so if your amp is fed from a high impedance source (like a volume pot!) there is some advantage over bipolars, but not over JFETs. Voltage noise-wise, they are the worst of the three, at least types i have used, but in a power amp, IMHO their other virtues outweigh the shortcomings. Unfortunately I am not in a position right now to offer measurements, other than the 'ear to tweeter' type, at the moment, so take this for what it's worth.
Bob Cordell said:
Don't expect MOSFET SPICE models to include noise modeling at all, after all most MOSFET applications are for power conversion or power source followers where noise is irrevelant. I have yet to see a discrete MOSFET datasheet with any en, in curves.
Heck, very few BJT models include noise that correlates with datasheets, most list KF=0, AF=1 (so 1/f is not modeled) and Rbb in the LTSPice model list are either 10 or 20 ohms which suggests guessing. The JFET models seem to be the exception here, with fairly good datasheet correlation.
In general do not trust SPICE models for noise, if possible verify them against measurements (if possible) or datasheet curves (if available) by simulating on a test circuit with predictable noise performance such as a current source loaded follower.
Perhaps Nelson Pass could share his knowledge on MOSFET noise here?
nuvistor said:
Thanks. I think your comments are right on target.
I think SPICE noise analysis involving JFETs and small-signal BJTs with decent models are useful for comparisons and design exploration, especially if 1/f results are not relied upon too much, but I agree that this is surely an area where the results need to be compared with the noise of a real circuit.
Cheers,
Bob
Without specific noise measurements on 510-9510 devices, we have nothing to compare to. I have done these measurements in the past, and the 1/f noise is not good, especially 2'd stage for phono stage preamps. . However for a power amp that is not equalized, I doubt that the A rated noise is effected much by a second stage that is 15 times away from the input.
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