Thank Nico. I'll defer to your experience and drop them from my version of this design. Have a good night
@mz543578854, You got me thinking about the VAS current and degeneration I used. It occurred to me that if the current was lowered, the dissipation would drop which reduces the temp at the junction. This in turn allows less degeneration to be used and still retain thermal stability.
Try these mods and let us know what you think. In your schematic from post #211:
Thanks for stirring the pot!
@mz543578854, You got me thinking about the VAS current and degeneration I used. It occurred to me that if the current was lowered, the dissipation would drop which reduces the temp at the junction. This in turn allows less degeneration to be used and still retain thermal stability.
Try these mods and let us know what you think. In your schematic from post #211:
- Change R4/R5 to 1K. Targeting for 1mA thru each JFET and 11mA to 12mA for the VAS. This also follows the VAS current Nico suggested.
- R8 to 5K and R7 to 1k. C5 can then drop to 100u or 220u.
- For Q3/Q4 I have 2SA1381E/2SC3503E in my sims. If using KSA1381E/KSC3503D, use 22R & 18R for R4 & R5.
- Drop C6/7 to 10pF. This provides a gain margin of 19dB & 68 degrees with ULG of 2MHz.
- Per discussion with Nico, eliminate C9/10, and D1 - D8
Thanks for stirring the pot!
Thank you Nico! Very elegant design refined to its simplest. I will ponder. Should I take you literally on the battery bias, that is a nice trick indeed. (I use this in a lot of my tube designs, but had not considered it for jfet bias - no intrinsic diode to deal with? I should know this... 😀 )
I have a reasonable quantity of 2SK170BL and 2SJ74BL, I am quite enthralled with them at the moment.
I have a reasonable quantity of 2SK170BL and 2SJ74BL, I am quite enthralled with them at the moment.
I actually did, a coin cell last years.Gate current is a few pico amps🙂
That's elegant, seems like an ideal solution. Has worked well in some phono stage applications for me. 😀
First iteration for the Ultra-amp. Next is a cascode version. Since I know (almost) nothing of what am am doing, I will look at other amp designs similar to lineup's, and try to copy their cascode parts. But here is take one! Did a few mods to see how they are received by the experts... 🙂
Just one question. Do you need all those potentiometers? I am sure you can get away with only RV4 and RV5. RV4 sets your bias and RV 5 the output off-set. You could even fix your bias with to about 100mA. I just think it may be a nightmare to adjust all those pots optimally. Also I would add the input ground lifting resistor about 10 ohms or so and a parallel capacitor of 100 nF or so just to avoid ground loop with external equipment.
I've been thinking about the VAS current and why I settled on 25mA originally. So, I decided to waste some time...
To assess this at different VAS currents fairly, you need to adjust the degeneration for each level. So I ran some sims with TTA004B / TTC004B for 20KHz at 25W with 600mA of bias. I used the higher frequency and output because any differences in THD will be more pronounced and easier to see at this level.
This does point back to 25mA as ideal for THD and 10mA as ideal for thermal stability. 15mA might be a good compromise between the two ends.
The cold to hot bias change is due to the VAS devices warming up. With SC3503 / SA1381, I would expect the cold to hot delta to be smaller due to their lower gain.
To assess this at different VAS currents fairly, you need to adjust the degeneration for each level. So I ran some sims with TTA004B / TTC004B for 20KHz at 25W with 600mA of bias. I used the higher frequency and output because any differences in THD will be more pronounced and easier to see at this level.
This does point back to 25mA as ideal for THD and 10mA as ideal for thermal stability. 15mA might be a good compromise between the two ends.
The cold to hot bias change is due to the VAS devices warming up. With SC3503 / SA1381, I would expect the cold to hot delta to be smaller due to their lower gain.
Yep - I choose consistent "10 x Re" degeneration for the sims to keep conditions equivalent.
So, I must have decided 25mA early on then increased degeneration to reduce the bias swings. However, it would probably be better to just lower the VAS current. Or lower the degeneration for 25mA to 12R and be OK with a bit more swing from cold to hot. 60mA of change isn't bad.
So, I must have decided 25mA early on then increased degeneration to reduce the bias swings. However, it would probably be better to just lower the VAS current. Or lower the degeneration for 25mA to 12R and be OK with a bit more swing from cold to hot. 60mA of change isn't bad.
BTW, I'm happy to see that there was some basis to the VAS current I choose - haha. Had me scratching my head last night trying to figure out why I picked that value. I had remembered it being purposeful.
Haha, of course! I reused an old drawing to give me a quick start. Here is the correct one:
RV3 trims the IPS current to account for JFET variations
RV5 trims DC offset
RV4 sets the OPS bias
What is the intention for RV1 & RV2?
If using multiple output pairs, Exicon sells selected pairs that are marketed as not needing source resistors for current sharing. I've never tried them, so can't say it if works in practice.
RV5 trims DC offset
RV4 sets the OPS bias
What is the intention for RV1 & RV2?
If using multiple output pairs, Exicon sells selected pairs that are marketed as not needing source resistors for current sharing. I've never tried them, so can't say it if works in practice.
Right! I realized I did not need RV1 and RV2 which were there in lineup's design. I guess RV5 takes care of that?
Current iteration of my PCB. Since the IRF vertical MOSFETs are looking that great in the sim, I changed to allow either Exicon or those.
Because the IRFs do not seem to have the gate-source protection diodes, I kept on the board.
Was able to reduce size to 50mm x 150mm.
The 3D-model of the TO-200 IRF is not showing correctly. Of course the would be under the PCB on the heatsink. Couldn't find one for KiCAD that matches that mounting.
Because the IRFs do not seem to have the gate-source protection diodes, I kept on the board.
Was able to reduce size to 50mm x 150mm.
The 3D-model of the TO-200 IRF is not showing correctly. Of course the would be under the PCB on the heatsink. Couldn't find one for KiCAD that matches that mounting.