In my head I calculate that with 24V rails you may get a peak swing of 20V which will give you 50 watt peak (I don't use r.m.s. watts, there is no such thing in engineering) so let is say average power of 25W into 8 Ohm more than enough. You can even include a bias switch to flick between lass A and AB, by change of a single resistor.
EDIT: Class A and AB output the same power at the same supply, only the class A will dissipate four times more heat. Therefore you need 4x the VA transformer.
EDIT: Class A and AB output the same power at the same supply, only the class A will dissipate four times more heat. Therefore you need 4x the VA transformer.
With 20V rails, you should be able to get 14W or 15W of output. And dissipation would be pretty reasonable. You could probably run this all in Class A with a 2U or 3U heatsink.
Thanks! I will make my own PCB, no problem.
With cascode I will loose voltage, so will there be a net gain?
Thanks Brian!
I was hoping for 24V, but 20V without cascode soundd like a good compromise. And it will fit in nicely between the Hiraga Monster 8W and Aleph 5.
Cascoding is just as easy, two more JFET one in each leg and they share the voltage across them. Just an example{
Easy for you to say! I have no experience with sim-SW and I am not able to calculate the needed values of resistors ec.
Is FET cascode better than BP?
Yes you will be able to get the designed power of the amp. Cascode swings double the voltage, you can relate it to a double long tail pair.
I was designing before simulators, I lay PCBs with black tape and graph paper.
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You have to have the netlist in your head, there was no PCs
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You have to have the netlist in your head, there was no PCs
My first layouts were made with inc pencils. The Hiraga Monster is still playing with this PCB after 30+ years!
It is astonishing what we could accomplish even in the early seventies. And it worked, mostly first time. All you had to your disposal was a data sheet and you HP35 calculator, and that was cutting edge.
Should be the opposite, the P channel have higher input capacitance, so match the time constant equaling the N channel with its lower C it would mean the P ch requires a lower gate resistor value, also, the N ch is much more prone to oscillation than the P ch (this was the case at least with the Hitachis) and is the one to look out for with regards to suitable gate resistor value.
I believe Nico was thinking right but got it upside down when typing it out.
Sorry, sh!t guys I am tired, had my P and N channels mixed up. Just realised it when I opened the data sheet.
Just to set your mind at ease Brian:
Just to set your mind at ease Brian:
The gate-drain capacitor usage is just based on my readings on these forums. I'm not smart enough with this stuff to make a case for it on my own. I seem to see repeated cases of designs with laterals having oscillation problems where the builders have added caps to resolve it.
Probably just me being paranoid with a new design that had not yet been built. When I build my next channel, I'll leave them out and see if any hints of oscillation show up.
These are some of the threads I recall seeing these caps described:
@RCruz in this this thread: Singleton Jfet Input with laterals.... very fast amp
@Transistorlegacy in this thread: Revisiting lateral MOSFET stability
Probably just me being paranoid with a new design that had not yet been built. When I build my next channel, I'll leave them out and see if any hints of oscillation show up.
These are some of the threads I recall seeing these caps described:
@RCruz in this this thread: Singleton Jfet Input with laterals.... very fast amp
@Transistorlegacy in this thread: Revisiting lateral MOSFET stability
Brian, I read these threads but they don't seem to know why they ae doing it. They just introduce another pole, besides they also still use external gate protection, so I am not even confused. I have literally designed with LatMOSFETS since Toshiba introduced them, not for my self but contract design. My current amp has been doing a good job since 2008. I have also in the past studied LatMOSFET design papers by guys in the LatMOSFET semiconductor manufacturing industry, none ever mentioned this external capacitor. The only time, and this is only what I am thinking is if the output seems to be a lot faster than the Vas and need some slowing down, but.... This was also when I read about the optimum bias point of a LatMOSFET being 100 to 103 mA for class AB. relevant to distortion and stability. Obviously nothing to do with class A or high bias,
I think this thread is progressing well and that good results will come from it and trust their will be some interest from the crowd if they are spoon fed to the last drop, i.e. Gerbers, BOMs, where to buy and group buys, else I find that if it is not handed on a plate interest is lost. So yes it is no 03:30 here and it is high time to get some shut eye. Thanks, enjoyed our chats.
I think this thread is progressing well and that good results will come from it and trust their will be some interest from the crowd if they are spoon fed to the last drop, i.e. Gerbers, BOMs, where to buy and group buys, else I find that if it is not handed on a plate interest is lost. So yes it is no 03:30 here and it is high time to get some shut eye. Thanks, enjoyed our chats.
Hi Nico, what is your preferred way to bias a fet cascode? Elegant solution to the Vds problem, what effect on open loop gain? Curious.. I have been using emitter follower (eek) buffered resistive voltage dividers and sometime LEDs or voltage references.
TBH I actually did not consider cascading jfets, and cascaded them with bjts in past designs. This seems like a brilliant idea. 🙂
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Goodness I should be asleep and here I still am. I am just going to show you what I have done with Hiraga Le Monster then you can scratch your head a little.
