The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator

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#3,944
Many thanks for this test.


May I ask if the first discroll gen was with an AT-Cut or the first SC-Cut (same case size than the the AT-Cut) ?


I found the Crysteck wording very accurate. One can experiment power decoupling below it with smd acrylic cap (FCA from Cornel Dublier advised) around 0.5 to 1 uF : it will give the plus of laidback described on the Acussilicon but without loss of details : in fact it will make it a good combo with a Ian Fifo that sounds a little too dry/light (powersupplies and their smoothing change also dramatically the sounding result being those test a very difficult exercice)


Thanks again also to the one that sent their toys for this big test : bravo 🙂
 
#3,945
dddac said:
Now that both my countries are kicked out of the European Championships, time for hobby again! I just published my clock test 3 on my blog website…


The Clock Tests (part 3) - DDDAC

Now looking forward to Italy - England 😀
Click to expand...

Hi Doede,

thanks for your new listening step, I look forward to the next.

Although I'm italian I don't believe Italy could reach the final, good team but without true talents.

Andrea
 
#3,946
diyiggy said:
Many thanks for this test.


May I ask if the first discroll gen was with an AT-Cut or the first SC-Cut (same case size than the the AT-Cut) ?


I found the Crysteck wording very accurate. One can experiment power decoupling below it with smd acrylic cap (FCA from Cornel Dublier advised) around 0.5 to 1 uF : it will give the plus of laidback described on the Acussilicon but without loss of details : in fact it will make it a good combo with a Ian Fifo that sounds a little too dry/light (powersupplies and their smoothing change also dramatically the sounding result being those test a very difficult exercice)


Thanks again also to the one that sent their toys for this big test : bravo 🙂
Click to expand...

And thank you for the very valuable tip of the extra decoupling!
uhm, AT/SC - Sure should have mentioned... My understanding is that this is the SC Cut (Stefan, if wrong correct me)
 
#3,948
Sure, that would be a good one to put on the bench as well !

Please make sure to send it in a way BREXIT and customs are not screwing this up. Not sure what the best way is to declare this... maybe I "buy" it from you for 10 Euro so you can you declare it as a sale for 10 Euro, than it will pass customs. In case they ask, I can always show the paypal payment for example
 
#3,949
Or i just send it as a 'gift'. Not sure which is the best way.

It runs on 6v6 and so I could send the psu aswell. I use a 'PFM flea that is fed approx 18vac to give enough headroom for the onboard 7812 reg and cap multiplier.

The clock is using u.fl but if you needed to solder on an SMA then fine......infact I shall send you the Ian fifo adaptor aswell.!
 
#3,957
And You have served beautiful proof of the way, mechanism of the totally FALSE reasoning that You do here.
The article (on the contrary to the purpose of misuse here..) is very nice, clear and reasonable. It clearly describes, repeats the difficulty but also the need of the PLL techniques applied, necessary for the reception of an external clock source.

WHICH IS A TOTALLY FALSE, FAKE CLAIM HERE.

We are swapping in different devices as local Master Clock, that is properly the single local clocking that he explaines the importance of.. No PLL clock recovery is happening here AT ALL, if that would have skipped under your radar..
So thank You, this was a refreshing introduction to the the applied trolling techniques...
 
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#3,958
As joseph said, correct me if I'm wrong but I think you misinterpreted the use and usage of the term "master clock" the article is talking about. The twtmc is about what the article mentions as internal clock, perhaps confusing bc it's located outside of the dac casing for most people here 😉

Greetings
 
#3,959
Have to agree with Joseph here, that article does not at all target the aspect of jitter. Rather, it discusses the need for synchronisation (slip...?) between digital units and its eventual impact on performance and SQ. Read the conclusion?

//
 
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