I simulated Tandem OS with several different front-ends (E.g. this one).
No problems at all, everything works right off the bat, with similar results.
So it looks like I'll be able to test this OS with all my front-ends (4 so far)...
Finalizing PCB, will place an order soon. Already have all the parts.
Now, I'm just curious:
a) will this Tandem OS work with Hexfet output?
b) can it be modified to work with both N-hexfets - something like I've seen in one of Steve's sims?
I have a lot of IRFP260 devices, and no idea what to do with them...
No problems at all, everything works right off the bat, with similar results.
So it looks like I'll be able to test this OS with all my front-ends (4 so far)...
Finalizing PCB, will place an order soon. Already have all the parts.
Now, I'm just curious:
a) will this Tandem OS work with Hexfet output?
b) can it be modified to work with both N-hexfets - something like I've seen in one of Steve's sims?
I have a lot of IRFP260 devices, and no idea what to do with them...
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I tried hexfets, they seem to work fine - but with the output V swing being far from rail-to-rail 🙂
0.0000000% Thd reported by LtSpice...
0.0000000% Thd reported by LtSpice...
In principle, for an accurate error-correction, Q10 should also be a MOSfet. The V to I characteristic of BJT's and MOSfets has (very) broadly the same look, which means that some error-correction is performed, but with a better match, the THD could be reduced even further (<0.00000%?).
It should be possible to use NMOS only, by inverting the configuration and using a CFP-like PNP + NMOS combo for the upper transistor.
This wouldn't address the relatively limited output swing though. It might be possible to use a boostrapping scheme, but combining it with the EC without disturbing it would be an interesting brain-twister....
Another possibility would be a Vto erasing scheme, like in the Circlomos
It should be possible to use NMOS only, by inverting the configuration and using a CFP-like PNP + NMOS combo for the upper transistor.
This wouldn't address the relatively limited output swing though. It might be possible to use a boostrapping scheme, but combining it with the EC without disturbing it would be an interesting brain-twister....
Another possibility would be a Vto erasing scheme, like in the Circlomos
A Vto-erasing scheme could work ~transparently, if well implemented: here, two 3.5V sources have been placed in series with the gates, and the adjustments required were minor: for the lower transistor, it is completely transparent (but it not very useful because of the 0.47R limitation), and for the upper one an adjustment in the bias resistor is required to keep Iq ~the same.
I have also tested a direct-drive of the MOS, and it also works: with all the mods, the THD remains 0.0000% (4ppb of H2 in fact).
With the direct drive, an adjustment of the bias current and G-S resistor would be required to maintain a sufficient speed.
Another example of Vto elimination is the EZ-mos:
https://www.diyaudio.com/community/...s-amplifier-for-beginners.336797/post-5763844
I have also tested a direct-drive of the MOS, and it also works: with all the mods, the THD remains 0.0000% (4ppb of H2 in fact).
With the direct drive, an adjustment of the bias current and G-S resistor would be required to maintain a sufficient speed.
Another example of Vto elimination is the EZ-mos:
https://www.diyaudio.com/community/...s-amplifier-for-beginners.336797/post-5763844
Thanks Elvee!
For for mosfet version, I could not get rid of C25. Without it, it's a big mess, even with sinus waves.
You said earlier that C25 was causing "significant peaking in frequency domain".
Not sure if you see any easy way to get rid of it in this version...
For for mosfet version, I could not get rid of C25. Without it, it's a big mess, even with sinus waves.
You said earlier that C25 was causing "significant peaking in frequency domain".
Not sure if you see any easy way to get rid of it in this version...
A problem is that sim and reality strongly disagree in this case: for the bipolar version, the presence of C25 saved the day in sim, but ruined it in reality.
The only way to know with the MOS version is to build one, and check its effect in real life; not a big deal, except that there could be problems with and without it.... but that's part of the fun with this hobby
The only way to know with the MOS version is to build one, and check its effect in real life; not a big deal, except that there could be problems with and without it.... but that's part of the fun with this hobby
This is all N-MOS version. Unfortunately IRFP260 are terrible at this application, these logic-level NMOS devices seem to be much better..
The problem with "C25" is that it is cross coupling as we discussed earlier, and I suggested a solution in post #28.
Well done! Exactly what I had in mind.
Now it's my turn to contribute.
This is the "zero-threshold" version. It is simply a memory cap paralleled with a LED, biased to have Vf=Vto. In a regular amplifier, this would be finnicky, because the voltage would have a major effect on the quiescent current, but with the tandem topology, the current is under control, and even a few hundreds mV change would only have a tiny effect.
At ~10µA, the tempco of the LED should crudely compensate the MOS (but it isn't critical anyway):
In the sim, I didn't actually use the synthesized Vg's, because this would probably involve long time constants, but if you compare the synthetic and actual values, you see that they are identical, meaning it should work in reality.
A minor remaining issue is the presence of D6: it is a power diode, and eats up one Vbe of output swing.
A possible solution is to use just the current sensing resistor and a low-power, diode-connected transistor like Steve did, but it is not very accurate or linear, and this would matter in the pure BJT version.
With a hybrid MOS/Bjt, the accuracy of the correction is not very good anyway, thus it does not matter too much.
It is possible to create a more accurate mirror, like I did in the BetaMaster project, but it is somewhat complicated
I didn't test this in reality, since the circuit works perfectly well without it. I do not see the need to make sim and reality agree, and it is not absolutely sure that it would work anyway.
In fact, two competing options are shown on the schematic: in reality, V5 and V6 should not exist in the real world, Vg1 should be connected to M1 and Vg3 to M3, but I opted for a fake circuit for the sim, because there are large time constants involved (100µ x 12Meg= 1200 seconds), and to be sure that the sim is actually accurate, it would need to run for X times 1200 seconds, + the 5ms of the useful sim, and even if you have an extra-powerful machine, the sim time would be prohibitive.
It might simulate alright with the default options -or not-, you might get it right by chosing the right startup conditions -or not-, and the only way to be sure is to run the real thing in good conditions: we are at 4~5ppb of distortion, and if there is the tiniest DC drift in the waveform, the THD analysis will be skewed.
In your sim, you have shorted C17 for the same reason; in some instances, such a cap could be replaced with a voltage source having a suitable voltage.
In our case, I took no risk: the load of the Vto-eraser is just the gate capacitance, and there is no risk of a leak or other disturbance, meaning the voltage source is a perfect dead ringer of the physical circuit.
When the situation is not that clear-cut, additional verifications could be required
It might simulate alright with the default options -or not-, you might get it right by chosing the right startup conditions -or not-, and the only way to be sure is to run the real thing in good conditions: we are at 4~5ppb of distortion, and if there is the tiniest DC drift in the waveform, the THD analysis will be skewed.
In your sim, you have shorted C17 for the same reason; in some instances, such a cap could be replaced with a voltage source having a suitable voltage.
In our case, I took no risk: the load of the Vto-eraser is just the gate capacitance, and there is no risk of a leak or other disturbance, meaning the voltage source is a perfect dead ringer of the physical circuit.
When the situation is not that clear-cut, additional verifications could be required
OK, this is an attempt to use two output pairs, I hope I got it right....
Thd and FFT looks minimally worse than for a single pair so I guess something is not optimal...
These output devices all small, so I guess 2 pairs is a must..
Thd and FFT looks minimally worse than for a single pair so I guess something is not optimal...
These output devices all small, so I guess 2 pairs is a must..
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It is OK. The value of R35 and R36 should be reflected in an increase of 11 ohm for R20, but we do not know the current optimum value, and this has to be determined on the completed amplifier.
I thought we should decrease R20, not increase... ??
It looks like R20 is still optimal at 1.8 Ohm (at least in the sim).
1.9 makes FFT profile slightly worse
1.7 has no effect, or perhaps minimally worse...
Mix of N and P output devices overall looks more stable and easier to sim than all N devices version.
Since it doesn't seem reasonable to use IRFP260 mosfets (I think I should give up on them for audio applications),
I guess there is no need for this configuration, at least for me.
And complementary mosfet version with FQAs can be built on the same PCB as BJT version, and gives excellent sim results..
It looks like R20 is still optimal at 1.8 Ohm (at least in the sim).
1.9 makes FFT profile slightly worse
1.7 has no effect, or perhaps minimally worse...
Mix of N and P output devices overall looks more stable and easier to sim than all N devices version.
Since it doesn't seem reasonable to use IRFP260 mosfets (I think I should give up on them for audio applications),
I guess there is no need for this configuration, at least for me.
And complementary mosfet version with FQAs can be built on the same PCB as BJT version, and gives excellent sim results..
R20 is "negativized" by Q14. When additional resistors are included in the sources, it has to be increased to compensate for them, in the same ratio as R17 and R19.
At least, that's the principle with a completely homogeneous circuit. With a mix of technologies, it's anyone's guess.
What is the main problem with IRFP260?
At least, that's the principle with a completely homogeneous circuit. With a mix of technologies, it's anyone's guess.
What is the main problem with IRFP260?
Higher distortion, more difficult to stabilize in sim ( I guess because of higher Gate capacitance),
from my experience more likely to oscillate in actual builds (multi-pairs), and much higher voltage drop.
I think these shortcomings are not specific only to this topology..
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