LTspice resolution to double precision
Thanks to the yahoo LTspice group, I now found the option needed to get double precision resolution (I knew they would have build that into the s/w):
.option numdgt=15
Now the internal sine source harmonics are down to about 1e-13. One then needs a very small time step though (10k...100k points per period), causing sim time and output data amounts to skyrocket...
Not that one would need that for any real world circuits, but sometimes it is useful. One might also need to adjust other options to really get that resolution.
- Klaus
Thanks to the yahoo LTspice group, I now found the option needed to get double precision resolution (I knew they would have build that into the s/w):
.option numdgt=15
Now the internal sine source harmonics are down to about 1e-13. One then needs a very small time step though (10k...100k points per period), causing sim time and output data amounts to skyrocket...
Not that one would need that for any real world circuits, but sometimes it is useful. One might also need to adjust other options to really get that resolution.
- Klaus
Japanese JFET models
These are some good models that I have used lately for the popular Toshiba JFETs. 2SK389 and 2SJ109 are simply dual 2SK170 and 2SJ74.
K170 and J74 models are set to an Idss of about 12mA while K246 and J103 are set to an Idss of about 6mA. For other Idss values, adjust the model BETA parameter. In a first approximation, BETA=Idss*Vto^2 where Vto is the threshold voltage, already defined in each model.
.model J2sk170 NJF(Beta=59.86m Rs=4.151 Rd=4.151 Betatce=-.5 Lambda=1.923m
+ Vto=-.5024 Vtotc=-2.5m Cgd=20p M=.3805 Pb=.4746 Fc=.5
+ Cgs=25.48p Isr=84.77p Nr=2 Is=8.477p N=1 Xti=3 Alpha=10u Vk=100
+ Kf=111.3E-18 Af=1)
.model J2sk246 NJF(Beta=1.07m Rs=56.76 Rd=56.76 Betatce=-.5 Lambda=2.8m
+ Vto=-2.638 Vtotc=-2.5m Cgd=10.38p M=.4373 Pb=.3905 Fc=.5
+ Cgs=6.043p Isr=112.8p Nr=2 Is=11.28p N=1 Xti=3 Alpha=10u Vk=100
+ Kf=1E-18 Af=1)
.model J2sj74 PJF(Beta=92.12m Rs=7.748 Rd=7.748 Betatce=-.5 Lambda=4.464m
+ Vto=-.5428 Vtotc=-2.5m Cgd=85.67p M=.3246 Pb=.3905 Fc=.5
+ Cgs=78.27p Isr=129.8p Nr=2 Is=12.98p N=1 Xti=3 Alpha=10u Vk=100
+ Kf=26.64E-18 Af=1)
.model J2sj103 PJF(Beta=2.197m Rs=76.76 Rd=76.76 Betatce=-.5 Lambda=735.3u
+ Vto=-2.037 Vtotc=-2.5m Cgd=18.95p M=.5045 Pb=.3905 Fc=.5
+ Cgs=17.02p Isr=38.48f Nr=2 Is=3.848f N=1 Xti=3 Alpha=10u Vk=100
+ Kf=1E-18 Af=1)
These are some good models that I have used lately for the popular Toshiba JFETs. 2SK389 and 2SJ109 are simply dual 2SK170 and 2SJ74.
K170 and J74 models are set to an Idss of about 12mA while K246 and J103 are set to an Idss of about 6mA. For other Idss values, adjust the model BETA parameter. In a first approximation, BETA=Idss*Vto^2 where Vto is the threshold voltage, already defined in each model.
.model J2sk170 NJF(Beta=59.86m Rs=4.151 Rd=4.151 Betatce=-.5 Lambda=1.923m
+ Vto=-.5024 Vtotc=-2.5m Cgd=20p M=.3805 Pb=.4746 Fc=.5
+ Cgs=25.48p Isr=84.77p Nr=2 Is=8.477p N=1 Xti=3 Alpha=10u Vk=100
+ Kf=111.3E-18 Af=1)
.model J2sk246 NJF(Beta=1.07m Rs=56.76 Rd=56.76 Betatce=-.5 Lambda=2.8m
+ Vto=-2.638 Vtotc=-2.5m Cgd=10.38p M=.4373 Pb=.3905 Fc=.5
+ Cgs=6.043p Isr=112.8p Nr=2 Is=11.28p N=1 Xti=3 Alpha=10u Vk=100
+ Kf=1E-18 Af=1)
.model J2sj74 PJF(Beta=92.12m Rs=7.748 Rd=7.748 Betatce=-.5 Lambda=4.464m
+ Vto=-.5428 Vtotc=-2.5m Cgd=85.67p M=.3246 Pb=.3905 Fc=.5
+ Cgs=78.27p Isr=129.8p Nr=2 Is=12.98p N=1 Xti=3 Alpha=10u Vk=100
+ Kf=26.64E-18 Af=1)
.model J2sj103 PJF(Beta=2.197m Rs=76.76 Rd=76.76 Betatce=-.5 Lambda=735.3u
+ Vto=-2.037 Vtotc=-2.5m Cgd=18.95p M=.5045 Pb=.3905 Fc=.5
+ Cgs=17.02p Isr=38.48f Nr=2 Is=3.848f N=1 Xti=3 Alpha=10u Vk=100
+ Kf=1E-18 Af=1)
I did the math, and using your formulas:
Idss*(1-(Vg/Vto)^2) = Beta*(Vg-Vto)^2
=>
Idss = Beta*(Vg-Vto)^2 / (1-(Vg/Vto)^2)
and - at Vg = 0 - that
Idss = Beta * Vto^2
Looking in the datasheet, I read that
Idss is dependant on Vto.
I copied the relavant part and attached it.
Tell me, where am I wrong.
Sigurd
Idss*(1-(Vg/Vto)^2) = Beta*(Vg-Vto)^2
=>
Idss = Beta*(Vg-Vto)^2 / (1-(Vg/Vto)^2)
and - at Vg = 0 - that
Idss = Beta * Vto^2
Looking in the datasheet, I read that
Idss is dependant on Vto.
I copied the relavant part and attached it.
Tell me, where am I wrong.
Sigurd
syn08 said:
Attachments
Sigurd Ruschkow said:
Idss = Beta * Vto^2 is valid at all Vg, it's an identity (again, in a very first approximation). In the graph you attached, scales are not linear. In linear scales, that graph is parabolic as predicted by the above formula.
You could also easily check the validity of the above formula using your favorite simulator. Connect the gate to the source and the drain to a DC source. Do a DC sweep analysis (0...5V) and watch the drain current saturate. The Id saturation value is Idss. Then modify Beta and see how Idss follows the above formula (Vto is defined in the model).
Syn08,
maybe we are talking about different hings here. I am talking about how to create JFET models that approximately correlate to the JFET's datasheet.
You are of course correct that if you vary Beta, Idss will change.
That is as Idss = Beta * Vto^2 (at VGS = 0),
but you can also vary Vto to get the same Idss value!
The formula Idss = Beta * Vto^2 is only valid for UGS = 0.
When UGS != 0, you will have to use the formula
Idss = Beta*(Vg-Vto)^2 / (1-(Vg/Vto)^2)
You say that Vto is in the model, that it correct. But how do you get that value? In SPICE you can get whatever Idss value you want just by changing Vto. No need to fiddle with Beta. But that will not give you real world JFETs.
I get Vto by looking in the datasheet, in the figure I attached in my previous post, by looking at what Idss my model shall have at VGS= and and VDS = 10V,
and then I get the Vto for that JFET from that figure. That Vto is then used in the model.
I then adjust both Beta and Lambda so that SPICE shows me the IDss value I wanted at VGS=0 and VDS = 10V.
Idss also depends on VDS. That is why the lambda parameter is there in JFET models.
There also temparature dependencies in Vto and Beta but I do not use that dependencie.
Sigurd
maybe we are talking about different hings here. I am talking about how to create JFET models that approximately correlate to the JFET's datasheet.
You are of course correct that if you vary Beta, Idss will change.
That is as Idss = Beta * Vto^2 (at VGS = 0),
but you can also vary Vto to get the same Idss value!
The formula Idss = Beta * Vto^2 is only valid for UGS = 0.
When UGS != 0, you will have to use the formula
Idss = Beta*(Vg-Vto)^2 / (1-(Vg/Vto)^2)
You say that Vto is in the model, that it correct. But how do you get that value? In SPICE you can get whatever Idss value you want just by changing Vto. No need to fiddle with Beta. But that will not give you real world JFETs.
I get Vto by looking in the datasheet, in the figure I attached in my previous post, by looking at what Idss my model shall have at VGS= and and VDS = 10V,
and then I get the Vto for that JFET from that figure. That Vto is then used in the model.
I then adjust both Beta and Lambda so that SPICE shows me the IDss value I wanted at VGS=0 and VDS = 10V.
Idss also depends on VDS. That is why the lambda parameter is there in JFET models.
There also temparature dependencies in Vto and Beta but I do not use that dependencie.
Sigurd
Sigurd Ruschkow said:
Sigurd,
For device physics reasons, the FET Id-Vgs dependency is, in a first approximation, parabolic.
For the particular case of a JFET (it's formally almost the same for depletion MOSFETs or enhancement MOSFETs, to an X axis translation) now imagine that x=Vg and y=Id.
By convention, the Vg at which Id=0 (well... almost 0) is defined as Vto. Also by convention, the drain current at Vg=0 is defined as Idss. Please note that these are definitions and they do not, by any means, depend on Vds or Vg or any other variable. This representation leads to an Id dependency to Vg as Id=Idss*(1-(Vg/Vt)^2).
You may chose another set of parameters, that is for example Beta and Vto. Such a representation tells more to the device physicist because Beta can be conveniently further identified (by writing the device physics equations) as a function of the device geometry and some other parameters (carriers mobilities, etc...). In this representation, Id=Beta*(Vg-Vt)^2
Please note that in the above we discussed two ways to write the same physical dependency of Id(Vg). Id(Vg) should be the same whatever representation you may chose, therefore the two representations should be identical. The only way to make them identical is to chose Beta=Idss*Vto^2
Now, again from a device physics perspective, Id(Vg) is parabolic in at least two simplifying circumstances: a) Vds is very small and b) mobility carrier degradation is neglected. We need more that two (Idss and Vto or Beta and Vto) parameters to model these phenomena. Here comes Lambda and the other parameters in the model files I've posted, but these are by no means impacting the Idss or Beta definitions.
The bottom line is that Vto and Idss (or Beta) are independent parameters that you have to extract in order to be able to model a JFET. Idss is something you could directly measure as I've mentioned in my previous post, so it is sometimes preffered by EEs. If you have Idss, then you may calculate Beta to plug into the spice JFET model.
Now, for Idss and Vto you have to choose some numerical values. The regular (and simple) approach is to chose Idss and Vto as the average values between the min and max in the datasheet. Another approach is to get the datasheet curves, digitize them, and do a best fit analysis to extract Idss and Vto and perhaps the other parameters (Lambda, etc...). This can be difficult, because you have to chose in advance the model you are fitting against. Depending of the chosen model, the best fitting (usually non-linear) process could be difficult and definitely could use some sort of computer aided help. Some simulators have the feature to let you enter the digitized curves and spit out the device model.
Datasheet curves are "typical" as much as the datasheet parameters have a certain dispersion (min...max). So in fact you are always simulating a "typical" or "average" case and for anything else you need either multiple simulations or the Monte Carlo method.
I hope this clears the muddy waters.
Re: Japanese JFET models
Hi,
I have the same models. Your definition, however, is not reflected there, if I'm not completly off anything.
For the 2SK170, it is stated BETA= 59.86m, Vto=0.5024, and you said Idss 12mA. When processing BETA=Idss*Vto^2
I get BETA=12*(0.5024^2)
BETA=12*0.2524=3.028m
Or, vice versa, if BETA is correct, you'd get an Idss of 237mA. Gosh!
I hope I don't mis-interprete the mathematical chars...
The relation of the modeled values are close to BETA=Idss*(Vto*10), however...
Rüdiger
syn08 said:
Hi,
I have the same models. Your definition, however, is not reflected there, if I'm not completly off anything.
For the 2SK170, it is stated BETA= 59.86m, Vto=0.5024, and you said Idss 12mA. When processing BETA=Idss*Vto^2
I get BETA=12*(0.5024^2)
BETA=12*0.2524=3.028m
Or, vice versa, if BETA is correct, you'd get an Idss of 237mA. Gosh!
I hope I don't mis-interprete the mathematical chars...
The relation of the modeled values are close to BETA=Idss*(Vto*10), however...
Rüdiger
Onvinyl said:Oops, I should have read your posts above
However, is it approprioate to leave anything but Vto and Idss unchanged in the model and hope for reasonability?
And, is there an obvious way to model thermal drift of the FET's parameters in LTSpice?
Rüdiger
I have checked those models against the datasheets and they are pretty good.
I have to confess I see little reason why simulating the Blowtorch, even if John would disclose the schematics. For the bias points, you don't really need to simulate anything (a calculator and ten minutes are good enough). For the noise performance - the models have no provisons for that, other than the thermal noise. For the closed loop bandwidth - it doesn't really matter if you are using K170/J74 or 2N5458/2N5461.
What's left:
The impact of device matching on the DC and AC performance. That's what I was mostly using the above models for. Yes, for this purpose you may want to keep Vto constant, and calculate Beta for (say) Idss=6, 10, 16mA.
The loop gain (if there's any feedback). The high gain of the japanese devices will pay off and, of course, the distortions (as much as you trust your simulator for that).
Don't expect a simulator to disclose why the Blowtorch is so highly regarded. To me, as much as I know about, if there's anything technically outstanding in the Blowtorch amp it's not the design/schematic, but the implementation/construction. As Scott Wurcer posted elsewhere, a simulator won't tell a thing about the difference (ahem... if there is any) between Vishay and Roederstein resistors.
Spice models suck big time when it comes to thermal analysis. You don't have any better chance but to create your own device models at different temperatures (if you have data about).
EDDELARUE said:Hi syn08,
Besides Toshiba Jfets models, would you have acurate models for 2SK1058/2SJ162 Hitachi Output Mosfets family , and/or their 2SK216/2J79 drivers family for use in Pspice ?
I wish... Unfortunately, the 2SK1058/2SJ162 datasheets are very, very poor so there's little to extract from there. So, until I'll get a curve tracer and a 1MHz (max) LCR meter with bias and HPIB, both sometimes later this year, use the following. They are horrible, but more than nothing...
.SUBCKT 2SK1058 10 20 40
* TERMINALS: D G S
* Hitachi 160 Volt 7 Amp .171 ohm N-Channel Power MOSFET 08-06-1993
M1 1 2 3 3 DMOS L=1U W=1U
RD 100 1 80.4M
RS 30 3 5.28M
RG 20 2 21.4
CGS 2 3 410P
EGD 12 0 2 1 1
VFB 14 0 0
FFB 2 1 VFB 1
CGD 13 14 128P
R1 13 0 1
D1 12 13 DLIM
DDG 15 14 DCGD
R2 12 15 1
D2 15 0 DLIM
DSD 3 100 DSUB
LS 30 40 7.5N
LD 10 100 4N
.MODEL DMOS NMOS (LEVEL=3 THETA=85M VMAX=163K ETA=2.2M VTO=.5 KP=.999)
.MODEL DCGD D (CJO=128P VJ=.6 M=.68)
.MODEL DSUB D (IS=29N N=1.5 RS=61.4M BV=160 CJO=802P VJ=.8 M=.42 TT=252N)
.MODEL DLIM D (IS=100U)
.ENDS
.SUBCKT 2SJ162 10 20 40
* TERMINALS: D G S
* Hitachi 160 Volt 7 Amp .171 ohm P-Channel Power MOSFET 08-06-1993
M1 1 2 3 3 DMOS L=1U W=1U
RD 100 1 110.4M
RS 30 3 25.28M
RG 20 2 17.4
CGS 2 3 760P
EGD 12 0 1 2 1
VFB 14 0 0
FFB 1 2 VFB 1
CGD 13 14 467P
R1 13 0 1
D1 12 13 DLIM
DDG 15 14 DCGD
R2 12 15 1
D2 15 0 DLIM
DSD 100 3 DSUB
LS 30 40 7.5N
LD 10 100 4N
.MODEL DMOS PMOS (LEVEL=3 THETA=90M VMAX=183K ETA=6.5M VTO=-.5 KP=1.109)
.MODEL DCGD D (CJO=467P VJ=.6 M=.68)
.MODEL DSUB D (IS=29N N=1.5 RS=61.4M BV=160 CJO=900P VJ=.8 M=.42 TT=252N)
.MODEL DLIM D (IS=100U)
.ENDS
gootee said:
3 years ago EDN had a design note in which the TL431 was used and the compensation network explicitly described -- the authors were two guys from Texas Instruments -- and had built a model for the TL431 --
It wasn't the model which TI has on its website -- the TI model correctly factors in the tempco of the device but is absent the reactive components.
I don't think that TI ever fixed the problem even though I talked to them and pointed out the incongruity. The ubiquitous TL431 costs about a nickel.
jackinnj said:
Is it this one? Note that I named it TL431EDN just to know from where I got this particular model for TL431.
*Reference3 Pin Order: A, K, Ref
*TL431 model from EDN magazine: March 15,1990, page 180-181
*Programmable Precision Reference pkg:TO-92 2,3,1. pkg_DIP8 6,1,8
*Connections
* Anode
* | Cathode
* | | Reference
* | | |
.SUBCKT TL431EDN 3 2 1
*
*Reference input stage
Q1 3 1 10 QINPUT
RIN 10 2 500K
*
*Internal reference voltage
VR 20 2 DC 1.7791
RVR 20 2 1G
*
*Pole/Zero modeling
GM 0 30 10 20 1
RGM 30 0 1MEG
*Pole/Zeros: Pole 1= RGM & CP2, 10KHz
* Pole 2= RP2 & CP2, 60KHz
* Pole 3= CP1 & RZ1, 500KHz
*
CP1 30 40 15.9P
RZ1 40 0 20K
RP2 30 50 10MEG
CP2 50 0 0.265P
*Gain stage voltage clamp
DC 0 30 DCLAMP
*
*Output stage
GO 3 2 50 0 2.5U
DR 2 3 DNOM
*
.MODEL DNOM D(IS=100E-15 RS=7)
.MODEL DCLAMP D(IS=0.1)
.MODEL QINPUT NPN (BF=1 VAF=11.15)
.ENDS TL431EDN
aparatusonitus said:
Yep, that's it.
The following model for the same circuit covers all of the temperature coefficient, AC gain, stability with capacitive loads (a big issue with TL431, and the reason why I prefer LM4041) noise and output impedance.
.SUBCKT TL431 A K R
Q1 3 2 1 0 NPN1 2.70
Q2 2 2 A 0 NPN1 1
R1 1 A 800 TC=0.00035
R2 4 2 2.4k
R3 4 3 7.2k
R4 5 4 3.28k
Q3 6 3 A 0 NPN1 1
R5 7 6 4k
Q4 10 5 7 0 NPN1 1
Q5 K R 5 0 NPN1 1
R6 2 12 1k
Q6 11 12 A 0 NPN1 0.2
Q9 K 11 13 0 NPN1 2
Q10 K 14 A 0 NPN1 10
R10 14 A 10k
R9 13 14 150
R7 K 8 800
Q7 10 10 8 0 PNP1 1
Q8 11 10 9 0 PNP1 1
D2 A K D1
D1 A 11 D3
R8 K 9 800
C1 K 11 20p
C2 6 3 20p
D3 11 R D2
.MODEL NPN1 NPN(Is=0.8e-14 BF=100 VAF=100 TF=0.5e-9 RB=50 IKF=10m KF=1e-16 AF=1 RE=10)
.MODEL PNP1 PNP(Is=1e-14 BF=50 VAF=50 TF=1e-8 IKF=2m KF=1e-16 AF=1)
.MODEL D1 D(Is=1e-13 Rs=10 CJO=20p)
.MODEL D2 D(Is=1e-13 Rs=10 CJO=2p BV=5 IBV=10u)
.MODEL D3 D(Is=1e-13 Rs=10 CJO=2p )
.ENDS TL431
john curl said:
Hi John Curl
Maybe my -so many time delayed- post appears in the eyes of some PC software management experts a little funny, because as i have seen already the subject have inclined from your first thought, the expression of your thougt and the mean of your thought.
First i have to declare -with each modesty that become in a declaration so i ask the forgiveness of anyone thinks that i am arrogant - that i am also an expert in any kind of CAD software. For my job, i use for 9 years the medium quality CAD-CAE "EDWin" of Visionics which is a complete suite from schematic drawing to spice-thermal-electromagnetic analyser. I have also the high value "Altium" from the time which named "Protel" but the EDWin appeared from the begining to suit better in my demands of work. The spice simulator of EDWin works just fine and i think it is not of lower value of any other software simulator. Moreover it has an open spice model library so we can write the parameters of any model we want. I remembered before 6 years when i asked from Motorola the model of two transistors, they answered to me-for my luck was a Greek fellow worked at Motorola-that they don't have the models, but the fellow he linked me in two university databases, and i remembered that the one was the Berkeley university from which i got the models finally. For 3 hours i filed the parameters in the library of the EDSpice simulator.
After little time passed, i discovered finally that, for my amplifier model the simulator gave -in any kind of input signal- a wonderfull flat response from 0 to 1MHz! Fantastic! Something goes wrong i thinked. I tried for 1 week with each trick to destroy this incretible beauty waveform, but nothing changed. I tried a demo amplifier circuit which included in the software -something like the Leach with the double LTP in input- and this time indeed the simulator indicated a fall of response of this amplifier around 100KHz. Also an obvious distortion TIM & THD. My amplifier circuit-a version of it i published the schematic in this forum before few months-was a prototype based a little in the D.Self propositions, in my knoweledge of the circuits of different P.A. amplifiers produced in your country, and in some experiments that i made for some years. My circuit was very advanced-CCS in each stage eliminating bootstraps, Current mirrors, tripple darlington output of course full complementary, shared resistors in conjuction with local feedback resistors in the output devices, large capacitor in the AC coupled feedback ground node, etc- and after the carefully inspection of the demo circuit i discovered that it was a purposely shoddy circuit to show the effectiveness of spice simulator. From then i use the simulator only in cases of computing the static currents with two voltage markers accross each resistor (that means via the voltage drop, there is not any practical way to measure directly the current) and this gives only by 80-90% correct results and only up to 120Volt split supply (from this point and above the precision drops abraptly!). Also the simulator can compute with relativelly good precision the output power for given loads, so we can margin the values of the summing network resistors of the VI limitter of output devices. That is all. Everything furthermore it is most for academic discusion. And the reason IMHO it is that; the simulator it supposes the models of all the devices active or passive as ideal! And in real world the things are absolutelly different! Of course i suppose that the spice simulator can show its value, but only if someone has the courage to measure separately and in two different (to place a margin in variations) ambient conditions each of the endless parameters (many of which need instruments found only in nuclear physics laboratories) of each device and fill the long list of the spice model of device. I think for a big circuit 1 month it is enough without sleep.
I close my lengthy post, by say that; As many measurements (such as THD+noise, frequency response etc) are for consumer purposes only, something that it is also the spice simulation i.e. for students. For combatant designers and constructors the clearest way of estimation it is the square wave in input from a good generator of 10MHz (in other words with very small rise time), a dummy load in output (clear resistive) and a DSO. From the shape of square in output you can estimate: 1)From the rise time the bandwidth of the project 2)From the shape of the duty portions of square all the types of distortion and noise 3)From the shape of tilt line (concave or straight) of the duty portion in very low frequencies (under 100Hz) the good or bad coupling of all local and of whole the feedback loop 4)From the amount of tilt again in the low frequencies the force of power supply, the low output impedance (if there is need for more output devices) and finally the tight control in bass reproduction (such the damping? Factor? What is this? It is eatable?).
With Respect
Fotios Anagnostou