Many thanks, but
A- I simply do not have the time to read through this document
B- It is not target-oriented at all to learn PLL basics for a one time occasion, adding SPDIF to a Sony CDP-101.
In order to light a candle in a church there is no need to become a monk.
Again, the solution is already there in the schematics above - I just need aid to use 16.9344MHz input instead of 4.2336MHz
and advice if all IC's are needed.
Many thanks! But I did describe this already in my very first post.
16.9344MHz is one possible strobe signal for the DIT4192 SPDIF digital transmitter
and divides almost evenly into 8.64MHz (output of A813 XTAL) by a factor of 1.96.
In the unaltered circuitry above the factor is 0.49.
Questions:
1- I assume the SN74LS368AN is fast enough to be fed by 16.9344MHz, the maximum is switching rate is 11ns = 90MHz. Correct?
2- Where in the circuitry do I divide 16.9344MHz back down to 4.2336MHz. Do I need to do this at all?
3- I would not need Pin3 A812 LRCK, which is 44.1MHz. PC2 Pin13 strobes 22,6µS, 44.247787610619 kHz.
(Philips schematics are just plain PITA. All numbers can be found in the CD-200 Service manual: https://elektrotanya.com/philips_cd200_sm.pdf/download.html pages 84 and 87)
Looks like P.L.L IC6664 HEF 4047 strobes 44.1 So I assume the IC on the far right SN74LS624N that provides 8.64MHz at pin 6 (A813 XTAL) does this based on a 44.1KHz Input signal? What role do the transistors BC558 play?
EDIT: Error in Philips Service Manual! It must be Pin 2 of HEF 4046. Pins 2 and 13 are phase comparator outputs.
Anyway, long story short:
Besides other things the circuit creates a 44.1KHz strobe in the first five ICs from a 4.2336 Mhz clock.
A ratio of 96:1. I assume this can be done much simpler.
Then, SN74LS624N (the IC on the far right, the name is missing) strobes the desired 8.64MHz
based on the 44.1KHz input created before. Correct?
If my findings / understanding is correct: 8.64MHz divides very uneven into 44.1kHz.
Ratio is 195,918367346938776
But 16.9344MHz divides very even into 8.64MHz.
Ratio is 1.96
So shouldn't it be wiser to design a PLL directly based on 16.9344MHz IN and 8.64MHz OUT?
Both would also run in sync, the basic function of a PLL, correct?
Anyway, long story short:
Besides other things the circuit creates a 44.1KHz strobe in the first five ICs from a 4.2336 Mhz clock.
A ratio of 96:1. I assume this can be done much simpler.
Then, SN74LS624N (the IC on the far right, the name is missing) strobes the desired 8.64MHz
based on the 44.1KHz input created before. Correct?
If my findings / understanding is correct: 8.64MHz divides very uneven into 44.1kHz.
Ratio is 195,918367346938776
But 16.9344MHz divides very even into 8.64MHz.
Ratio is 1.96
So shouldn't it be wiser to design a PLL directly based on 16.9344MHz IN and 8.64MHz OUT?
Both would also run in sync, the basic function of a PLL, correct?
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As you do not wish to become a monk may I suggest a circuit that does not require you to, at the very least, get a strange haircut.
The idea of a PLL is that a target frequency tracks a reference frequency. In this case of the CDP-101 the reference would be LRCK from CX7934 at 44100Hz. This would be compared with a 44100Hz signal derived from the target frequency VCO or VCXO. Such a circuit can be found in the Pass D1 schematic. It uses a difficult to obtain dual VCXO but it can be replaced with the kind Tentlabs may or may not still sell.
The idea of a PLL is that a target frequency tracks a reference frequency. In this case of the CDP-101 the reference would be LRCK from CX7934 at 44100Hz. This would be compared with a 44100Hz signal derived from the target frequency VCO or VCXO. Such a circuit can be found in the Pass D1 schematic. It uses a difficult to obtain dual VCXO but it can be replaced with the kind Tentlabs may or may not still sell.
In the Philips CD-303 / CD 200 example, Philips had to derive LRCK and LRCK for the rest of the Philips-based circuitry (not pictured) anyway.
As a result, they used 44.1KHz LRCK as as reference to sync the 8.64MHz clock of CX7934 to it.
Stil the reference or master was the 4.2236MHz at the beginning of the chain. If it runs 5% too fast, the LRCK would run 5% too fast as well.
Is this thought correct?
So I would like to use a 16.9344 clock (i already have one) needed for the transmitter as reference for 8.64MHz.
As a result, they used 44.1KHz LRCK as as reference to sync the 8.64MHz clock of CX7934 to it.
Stil the reference or master was the 4.2236MHz at the beginning of the chain. If it runs 5% too fast, the LRCK would run 5% too fast as well.
Is this thought correct?
So I would like to use a 16.9344 clock (i already have one) needed for the transmitter as reference for 8.64MHz.
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The 8.64MHz does not come from the 4.2236MHz. The 4.2236MHz simply provides the reference Fs at 44100Hz. The VCO provides the 8.64MHz for the CX7934 which in turn provides LRCK also at 44100Hz. The PLL compares the two 44100Hz signals and does what adjustment it needs to make to the VCO such that the two 44100Hz are in sync. That is how the CX7934 tracks the 4.2236MHz system clock while at the same time being in its own clock domain.
Alas, this is the reverse of what the CDP-101 requires. The DIT needs to track the CX7934. The CX7934 will effectively be providing the 44100Hz reference in the form of LRCK that the 4.2236MHz was providing in the Philips players.