Dear friends,
I did this before, adding an SPDIF to a second or third generation,
Sony-based player, using a Ti DIT4192 transmitter.
See this link how I did it with a Sony-based Nakamichi OMS-5EII 17 years ago (Really? Gosh!)
The Nak still plays my CD's every day!
Everything seems to be there in the Sony CDP-101 to achieve SPDIF-Out:
Data / Bitclock / R-L Clock to feed a DIT4192 for converting to SPDIF.
BUT:
The DIT 4192 needs a standard 19.9344 mHz frequency.
Normally no problem, as players with Sony circuits have a divideable of this frequency on board.
As one example, early players used 4.2336mHz (1/4) or 8.4672mHz (1/2), directly provided by a crystal.
Also 19.9344 mHz became very quickly common, or later multiples of it, like 67,7376 mHz.
So a Flip-Flop can be used to derive 19.9344 mHz from the mentioned frequencies and as far as I know
4.2336mHz and its multiples are a must to make a player work.
But being a first generation model, it looks like the Sony CDP-101
does not use a crystal with any of those frequencies.
The service manual
https://elektrotanya.com/sony_cdp-101.pdf/download.html
states the Xtals X501 and X502 are 8.6mHz and 35.022mHz - both frequencies are not multiples of 4.2336mHz
So I assume the base frequency is generated somewhere in the circuitry using PLL.
No hint in the service manual that 4.2336mHz exists (again, AFAIK it must) or where to measure and where grab it.
Does anyone know where 4.2336mHz can be found in this player?
BTW, the CDP-101 should trick audiophiles - there is damping above 15kHz and a delay between channels - it makes the CDP-101 sound "bigger".
All the best,
Salar
I did this before, adding an SPDIF to a second or third generation,
Sony-based player, using a Ti DIT4192 transmitter.
See this link how I did it with a Sony-based Nakamichi OMS-5EII 17 years ago (Really? Gosh!)
The Nak still plays my CD's every day!
Everything seems to be there in the Sony CDP-101 to achieve SPDIF-Out:
Data / Bitclock / R-L Clock to feed a DIT4192 for converting to SPDIF.
BUT:
The DIT 4192 needs a standard 19.9344 mHz frequency.
Normally no problem, as players with Sony circuits have a divideable of this frequency on board.
As one example, early players used 4.2336mHz (1/4) or 8.4672mHz (1/2), directly provided by a crystal.
Also 19.9344 mHz became very quickly common, or later multiples of it, like 67,7376 mHz.
So a Flip-Flop can be used to derive 19.9344 mHz from the mentioned frequencies and as far as I know
4.2336mHz and its multiples are a must to make a player work.
But being a first generation model, it looks like the Sony CDP-101
does not use a crystal with any of those frequencies.
The service manual
https://elektrotanya.com/sony_cdp-101.pdf/download.html
states the Xtals X501 and X502 are 8.6mHz and 35.022mHz - both frequencies are not multiples of 4.2336mHz
So I assume the base frequency is generated somewhere in the circuitry using PLL.
No hint in the service manual that 4.2336mHz exists (again, AFAIK it must) or where to measure and where grab it.
Does anyone know where 4.2336mHz can be found in this player?
BTW, the CDP-101 should trick audiophiles - there is damping above 15kHz and a delay between channels - it makes the CDP-101 sound "bigger".
All the best,
Salar
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Why? (BTW, that should be MHz for MegaHertz; mHz is for milliHertz).
DIT4192 Datasheet lists the clock frequencies it can use for a 44.1kHz sample rate:
Moreover, you could use a different part, such as AK4137, if you don't want to use a master clock (although SQ tends to be better with a crystal clock as opposed to using a PLL).
May I ask if you have an oscilloscope?
You're right about AK4137. Maybe take a look at SRC4392. IIRC it can use a crystal reference or not. Better with one however. You can provide your own reference clock though since its an ASRC. Doesn't have to be a crystal in the CD player.
All that having been said, why bother with CD players anymore? There are better ways...
All that having been said, why bother with CD players anymore? There are better ways...
Not necessary to find an internal CD player clock if you use an ASRC chip. You can use your own proper crystal clock or an ASRC chip built-in PLL. Your choice. Also, it may take more than one chip to fully implement, but its not a hard problem to solve.
However bit-perfect ripping will be much better in the long run. Just backup your data so it doesn't get lost. There is an online database of CDs to help with automated labeling of rips. That way you won't have the SQ loss problems associated with SPDIF or with ASRC. With a good dac you will be able to hear the difference in SQ, and I don't mean a type of dac you might be thinking of.
However bit-perfect ripping will be much better in the long run. Just backup your data so it doesn't get lost. There is an online database of CDs to help with automated labeling of rips. That way you won't have the SQ loss problems associated with SPDIF or with ASRC. With a good dac you will be able to hear the difference in SQ, and I don't mean a type of dac you might be thinking of.
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If I ask how to get to Sesame St., I really don't want to be told I'd better off going to Bedrock.
Dear Markw4, I would propose to you not to hijack this thread to expose your own beliefs but give answers according to the subject clearly stated in the thread’s title. I have a frequency counter and there are some candidates in the circuitry to check. As there is an on Chip PLL next to the 8.6mhz xtal, I assume the 4.2336mhz are produced there. I do not have the service manual in front of me for the moment.
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You know as well as I do the signal the OP is looking for may or may not be practically accessible. It may only exist inside of one chip, and or it may not be at a frequency easily compatible with DIT4192. Its not even confirmed what the actual I2S bus frequencies are.
Speaking of people asking wrong questions, I got asked for the make/model of a USB board that could plug into a ADSP21489 board and just work without having to know anything about programming or engineering design. Seems the fellow had been plugging USB boards and dacs together and it just happed to work. So he figured the same should be true with a USB board and ADSP21489. He just wanted to know which USB board he needed to get. How are you supposed to respond to that question in a way the person intended?
How about this: "Be careful CDP101 has two clocks one 8.6Mhz.for the DAC and strange (never seen it in other cd players) 35.022Mhz in the filter switching stage."
https://audiokarma.org/forums/index.php?threads/sony-cdp101-modification.213102/post-2632292
8.6MHz looks a little unusual. For example, not on the Tentlabs list at: https://www.tentlabs.com/Components/XO/index.html Well, unless maybe they meant 8.4672MHz?
Scope or maybe frequency counter might be used to show what the actual frequency is?
https://audiokarma.org/forums/index.php?threads/sony-cdp101-modification.213102/post-2632292
8.6MHz looks a little unusual. For example, not on the Tentlabs list at: https://www.tentlabs.com/Components/XO/index.html Well, unless maybe they meant 8.4672MHz?
Scope or maybe frequency counter might be used to show what the actual frequency is?
Hmmm...
8.6436MHz / 44.1kHz = 196(fs)
Prime factors of 196 are 2 × 2 × 7 × 7, which suggests they are using, what, a 14-bit dac? 14-bits x 2-channels = 28-bits/word. So, what is the other 7 for? 7x oversampling to get 16-bits equivalent?
EDIT: Schematic says dac chip is CX20017, which is 16-bits. Strange.
EDIT2: The other clock, 35.022Mhz, has prime factors of 2^4 x 3^1 x 5^3 x 13^1 x 449^1. So at least there is a 16 in that.
EDIT3: Looks like CX9333 is a 14-bit demodulator. Is it that the front end works at 14-bits, and its then oversampled to get 16-bits?
8.6436MHz / 44.1kHz = 196(fs)
Prime factors of 196 are 2 × 2 × 7 × 7, which suggests they are using, what, a 14-bit dac? 14-bits x 2-channels = 28-bits/word. So, what is the other 7 for? 7x oversampling to get 16-bits equivalent?
EDIT: Schematic says dac chip is CX20017, which is 16-bits. Strange.
EDIT2: The other clock, 35.022Mhz, has prime factors of 2^4 x 3^1 x 5^3 x 13^1 x 449^1. So at least there is a 16 in that.
EDIT3: Looks like CX9333 is a 14-bit demodulator. Is it that the front end works at 14-bits, and its then oversampled to get 16-bits?
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Still thinking about it, but too late to edit last post. I would probably delete EDIT3 at this point. Don't know enough about how these old CD players work. However, suspect there is no MCLK signal easily compatible with DIT4192. I2S bus does not include an MCLK signal. However, an MCLK can be recovered from the I2S frame clock using an PLL. Unfortunately SQ is not usually optimal that way. Better SQ is possible using an ASRC to resample I2S bus using a crystal clock attached to the ASRC chip. An ASRC could then also include a SPDIF output.
That's basically back to what I suspected earlier when when I suggested ASRC. However, even in that case the dac used to play back the resulting SPDIF stream might have another ASRC (at least if its a better dac, or if it uses an ESS chip). Two passes through ASRCs, plus the added jitter of SPDIF, doesn't seem that appealing to me. But I do know for a fact its possible to absolutely fabulous SQ from CDs using a discrete resistor DSD dac and conversion of PCM -> DSD256. Incredibly good sound if done right. So, I'm also back to what I was thinking about earlier, which is basically that its probably time to move past modifying old CD players to get slight improvements in SQ. Thus, I will continue to rip my collection.
That's basically back to what I suspected earlier when when I suggested ASRC. However, even in that case the dac used to play back the resulting SPDIF stream might have another ASRC (at least if its a better dac, or if it uses an ESS chip). Two passes through ASRCs, plus the added jitter of SPDIF, doesn't seem that appealing to me. But I do know for a fact its possible to absolutely fabulous SQ from CDs using a discrete resistor DSD dac and conversion of PCM -> DSD256. Incredibly good sound if done right. So, I'm also back to what I was thinking about earlier, which is basically that its probably time to move past modifying old CD players to get slight improvements in SQ. Thus, I will continue to rip my collection.
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I can't find any trace between CX7933 (Demodulator) and X502 that indicates that CX7933 is directly clocked by X502.
Also the problem we face is only part of the very first generation of players from Sony.
With the standardization by the CX20108, CX20109, CX23035, CX23034 chipsets already in 1984,
frequencies like 8.4672MHz suitable for upgrading to SPDIF became standard.
And those chipsets were in 80% of the players sold back then, also Kenwood, Accuphase, Nakamichi, Harman...
In the third generation, SPDIF was on board anyway.
Also the problem we face is only part of the very first generation of players from Sony.
With the standardization by the CX20108, CX20109, CX23035, CX23034 chipsets already in 1984,
frequencies like 8.4672MHz suitable for upgrading to SPDIF became standard.
And those chipsets were in 80% of the players sold back then, also Kenwood, Accuphase, Nakamichi, Harman...
In the third generation, SPDIF was on board anyway.
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If the goal is to find some way, any way at all, to get SPDIF out of this CD player, its likely possible. If might involve making a little PCB with a few ICs on it though. Maybe 3 -5 ICs. Something like that. It would probably also involve ASRC of the exposed I2S bus. This assumes it can be verified that the data format on I2S bus is a supported one.
It might also be possible to synthesize a MCLK for DIT4192 from the 8.6436MHz clock which if not perfect would at least close enough to the right frequency to work. Maybe. Again, this would probably be a little bit complicated too because most N/M rational fraction frequency synthesizers are probably 3.3v, etc. Also, it would probably make sense to verify the I2S bus protocol before going too far to make sure it will be supported.
Or maybe it would be more direct to use a PLL to generate an MCLK that is synced to the I2S bus frame clock. Maybe more jittery, but at least the right frequency.
It might also be possible to synthesize a MCLK for DIT4192 from the 8.6436MHz clock which if not perfect would at least close enough to the right frequency to work. Maybe. Again, this would probably be a little bit complicated too because most N/M rational fraction frequency synthesizers are probably 3.3v, etc. Also, it would probably make sense to verify the I2S bus protocol before going too far to make sure it will be supported.
Or maybe it would be more direct to use a PLL to generate an MCLK that is synced to the I2S bus frame clock. Maybe more jittery, but at least the right frequency.
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