I 100% agree with you - I dont understand how anyone can say otherwise when the numbers speak for themselves!!!
Also using the SI PN application, you can see the extra spurie due to the internal PLL Reference Clock "beating" with the Generated clock... this is REALLY not nice!
Everyone knows that fixed oscillators can be better, but the point of the Si parts is that the frequency is variable.
It alla depends if you want to optimise on delay (movie) or sound (Audio SOTA) or maybe save on memory BOM.
//
//
You then just show me a variable oscillator, preferable digitally controlled, that don't use too much power, are inexpensive and small.... Because I couldn't find any other meeting those requirements....
Everything is relative, the dam1021 still sounds good when using the Si514....
The dam1021 / 1121 ins't bad at all - for sure. I love mine. But I have yet more to spare 😉
//
//
I'm not Merlin the Magician, I'm not arguing about the cost, the power consumption and the size of the Si514. Of course it's cheaper and smaller than a BVA, but it remains a bad performing oscillator, the link you posted states clearly its short term instability, that's what we are looking in digital audio.
As TNT said it depends on what you are looking for, it could be the best compromise for movie streaming, but it's very poor for digital to analog conversion.
BTW you don't need a variable oscillator, you simply need a pair of decent oscillators, one for each sample rate family, maybe selected via relays to avoid any digital interference (the FPGA can easily do the job). But if you mean using the PLL of the Si514 to act a sort of frequency tracking to balance a very small FIFO, then I have to confirm what JohnW has already said: the PLL of the Si514 is a truly disaster.
I assume that the switches of your DAC are driven by the latch enable of the 595s, so this is the most important signal from the timing point of view because it represents the precise moment when the data stored in the registers are latched in the flip-flop.
The best way to do this is starting from a good oscillators and then divide down using a low phase noise divider outside of the FPGA, better if the divider is optically isolated from the FPGA that sets its division ratio depending on the sample rate.
Andrea sells fixed oscillators 🙂
And Andrea, somewhere you need to digest the difference between your fixed osc and the variation of the incoming bit-stream...
The PLL is implemented in FPGA I believe.
//
And Andrea, somewhere you need to digest the difference between your fixed osc and the variation of the incoming bit-stream...
The PLL is implemented in FPGA I believe.
//
Firstly: I don't sell anything. I share my projects with the diy community, complete schematics, board layouts and so on. I arrange GB to get good crystals and boards when MOQ is mandatory, and often I loose money rather than do a business. No commercial devices. Everyone is free to get crystals and boards to build himself the oscillators.
Audio is an hobby for me, I have no commercial interest to sell my projects.
Then the variation of the incoming bit-stream is easily managed by the FPGA that converts the incoming data to be presented at the input of the R2R DAC and generates the appropriate bit clock, whatever you want, with dithering or truncation or zero trailing. This variation does not means that you have to implement a variable oscillator, a fixed oscillator do easily the job providing the timing to the FPGA, simply its frequency has to be greater or equal to the output bit clock that feeds the DAC.
Finally, the latch enable is a signal at low frequency, in the range between 44.1 kHz and 384 kHz, so it can be simply derived dividing down the master clock directly from the oscillator and outside of the FPGA that provides the control of the dividing ratio depending on the incoming sample rate.
So there is no reason to use a variable oscillator with very poor performance in a R2R DAC where all the switches change their state when the latch goes enabled.
I believe instead that the Si514 is digitally controlled by the FPGA to track the incoming clock frequency, since the FIFO is very small and so it needs to be balanced continuously to avoid overflow or empty states. This means that the Si514 changes continuously the output frequency using its PLL.
Last, any PLL adds jitter because it modulates the clock frequency adding short term instability, so it should be avoided anyway in digital to analog audio conversion.
Last edited:
You're completely wrong that you can use fixed clocks, and the latch clock is the most important clock.... Sorry, you seems to know oscillators, but not much about digital audio....
The design of the dam1021 is based on a variable oscillator, you need that when using a small FIFO and the digital PLL to track incoming sample rates. If you think people are complaining a little now, then figure what would happen if I used your way of controlling the clock, talk about jitter by dropping clock pulses....
The dam1021 has been designed to be flexible and easy to use, so no long FIFO, don't work with video or live settings, it can tolerate crappy clocks, like SPDIF sources or the RPi.
Last edited:
OK, far point, I can look at working on a small circuit for you - what clock frequency do you need? We can use a small I2C DAC for Frequency control.
As I guess you will need atleast +/- 100ppm pull then a Colpits with its lower in circuit Q over the Driscoll / Healey is your best bet.
I dont know what PCB area you have for upgraded clocks ...
Søren,
I must aplogise, I did not realise that this was a commercial project - I didn't know the DAC design (I spoke without reading though the various threads) - my post was just intended as passing comment about the PN of the PLL based SI parts as I've encountered these parts in the past.
Its very VERY nice to see "real" design work rather then simply plonking down "off the shelf" DAC IC's 🙂 - rare to see such hardwork thesedays, and as you say I'm certain that sonically the design blows other IC based designs out of the water 🙂
I'd be more then happy - even excited to work on the clock circuit for you (always keen to "hear" how far a design can be pushed - its part of life's constant learning process 🙂 ) - but I would rather keep the clock circuit unpublished as it would be almost certainly copied by "Chinese" DiY kit manufactures who seem to frequent this forum and shamelessly "Commercial" the hard work of the DiY community!
I must aplogise, I did not realise that this was a commercial project - I didn't know the DAC design (I spoke without reading though the various threads) - my post was just intended as passing comment about the PN of the PLL based SI parts as I've encountered these parts in the past.
Its very VERY nice to see "real" design work rather then simply plonking down "off the shelf" DAC IC's 🙂 - rare to see such hardwork thesedays, and as you say I'm certain that sonically the design blows other IC based designs out of the water 🙂
I'd be more then happy - even excited to work on the clock circuit for you (always keen to "hear" how far a design can be pushed - its part of life's constant learning process 🙂 ) - but I would rather keep the clock circuit unpublished as it would be almost certainly copied by "Chinese" DiY kit manufactures who seem to frequent this forum and shamelessly "Commercial" the hard work of the DiY community!
Last edited:
Nautibuoy, I am researching to find best way for I2S source to DAM1021. Hope to have your advice. Considering 02 options
1. USB (I consider it as easy way): Tried WaveIO and found it is good. Have you compare/or know if JLSound is better/worse than Wave IO?
2. Network + direct I2S: Considering between RPI+Ian FifoPI Ultimate and Beagle Bone Black. Also consider this (eRED-DOCK network audio interface - electronic, engineering and consulting)
I really want to try Network way (especially BBB, but RPI with Ian Fifo seem a easier solution), but my priority is sound quality, so I will follow whichever way can archive that.
Thank you.
OK, sorry for that - my mistake!! I should have know better as I have purchased a clock from you. Please forgive me.
//
s/pdif may, due to its low BW, have high intrinsic jitter. But it really is jitter - meaning deviation < UI (a clock cycle). If a really good low pn (< -110dbc @ 10hz?) clock drives the s/pdif, a very short buffer, e.g. say 5 clock cycles to be safe, would consume all those variations. It's tangent wander absorption (deviation > UI).
Well, well... at least Sören, maybe consider 2 modes; Movie and Music where Music requires a really stable source or it would go out of lock (and mute + blink).
//
I do wish there is a modification able to improve the clock jitter performance of dam1021. Since dam1021 controls a variable-freq clock chip by firmware, just HW mod seems not feasible.
Last edited:
That question was aimed at ditmfuk...
I wouldn't hold my breath if I where you. My take is that Sören is perfectly well equipped to design a clock solution with higher technical characteristics. But I don't think he wants or feels he need to. He doesn't need any help with it.
//
I wouldn't hold my breath if I where you. My take is that Sören is perfectly well equipped to design a clock solution with higher technical characteristics. But I don't think he wants or feels he need to. He doesn't need any help with it.
//