R1 is 6R8. All values are like this
http://www.diyaudio.com/forums/attachment.php?s=&postid=1722356&stamp=1232753798
except for the zener that I use, 1n4759a.
http://www.diyaudio.com/forums/attachment.php?s=&postid=1722356&stamp=1232753798
except for the zener that I use, 1n4759a.
salas said:
Hi Salas
I did not populate the board yet because I need to figure out some details. I have been checking the pcb and everything seems ok regarding the mosfets and NPN.
I can not figure out where Drain and Source are on the 2SK170 in your design
Are Drain and Gate connected together ? If so the Source connects to R4...
Ricardo
Nico,nicoch46 said:
B only suits a single rectifier and the Shunts must be a +ve & -ve pair.
A is OK with dual rectifiers and OK with a pair of +ve shunts or mixed +ve & -ve shunts or a pair of -ve shunts.
The resistors marked ? should be 0r0.
There was a thread suggesting that Inductors in the returns would work better, but I cannot recall the conclusion.
Hi,
for these Nchannel jFETs the Drain is the more positive connection and the Source is the more negative connection, i.e. D @ Top and S @ Bottom.
However, most jFETs are made such that they are truly symmetrical, i.e. one can swap D & S without affecting performance.
When the Gate is connected to Source, the jFET operates as a CCS and passes Idss from Drain to Source. It will try to operate over the range of ~ Pinch Off voltage to Vdsmax.
But watch dissipation of high Idss devices with high Vds. They will overheat to destruction. A gr with 25Vds and passing 3mA, dissipates 75mW<<400mW Pdmax.
A v device with 20Vds and passing 15mA dissipates 300mW and this will overheat the junction if Ta>=50degC.
for these Nchannel jFETs the Drain is the more positive connection and the Source is the more negative connection, i.e. D @ Top and S @ Bottom.
However, most jFETs are made such that they are truly symmetrical, i.e. one can swap D & S without affecting performance.
When the Gate is connected to Source, the jFET operates as a CCS and passes Idss from Drain to Source. It will try to operate over the range of ~ Pinch Off voltage to Vdsmax.
But watch dissipation of high Idss devices with high Vds. They will overheat to destruction. A gr with 25Vds and passing 3mA, dissipates 75mW<<400mW Pdmax.
A v device with 20Vds and passing 15mA dissipates 300mW and this will overheat the junction if Ta>=50degC.
could be, since the second regulator I built point to point still shows the same ripple on the output. I'll try hooking up the jfets as you say. I too thought they were symmetrical.