I have a power amp project that draws 105mA per channel and would really like to finally use my SSHV2 boards 🙂. I've had a look for confirmation of the current capacity but this is one long thread!
The build guide PDF gives a maximum current of 110mA - does this include the required spare 20mA (i.e. a usable current of 90mA for the load) and I'm out of luck? Or is it 110mA for the load?
The build guide PDF gives a maximum current of 110mA - does this include the required spare 20mA (i.e. a usable current of 90mA for the load) and I'm out of luck? Or is it 110mA for the load?
No, its a total. If you will use 1R T.P. resistor instead of 10R some DN2540 may give you 125mA as Q2 in this cascode VDS allowance depending on intrinsic IDSS per sample. In such a case the reading across T.P. should be interpreted 1mV=1mA. You should test the CCS in LV mode with say 15V across input by only tying force+ and force 0 together so to determine your new practical max. If its enough, use dummy load calculated and connected as in the manual description and attempt HV test of the whole circuit.
Thanks Salas, sounds like I'd be pushing it.
Silicon isn't my 'thing' and I might be missing the bigger picture but I have some IXTP08N100D2 - if I were to use these in the CCS instead of the DN2540 might I squeeze a little more current? Sorry, I don't mean to deconstruct your circuit.
Silicon isn't my 'thing' and I might be missing the bigger picture but I have some IXTP08N100D2 - if I were to use these in the CCS instead of the DN2540 might I squeeze a little more current? Sorry, I don't mean to deconstruct your circuit.
Its not a bad device, just slower. Do your tests first on LV with any devices at hand both as Q1 & Q2 or as a mix. In any case make sure your sink is up to the task especially if peak current at the true load is not that frequently demanded. Allow for full sinewave draw before clip.
Theoretically it could. But dangerous for failures to combine wide bandwidth regs in HV. Haven't tried it.
Yes, that's why I wondered about using a higher current part than the DN2540, then I could keep it simple and use the boards without too much alteration. Not sure quite what might happen if I paralleled CCSes?
Yes, I take your point. Better to lower the operating point if I can't squeeze enough current from the CCS I think.
You can create the CCS part on a breadboard and try your Ixys with say 20V across. Those are 800mA Idss parts they should give you enough current. Can predetermine a fixed Q2 source pin setting resistor value for each cascode pair of samples for your target current even. You will not need torturing the PCB with investigative tests that way.
Well, the DN2540 can give up to above 120mA (of course some wont). Mine give approx 110mA with 10R measure resistor, which mean it will give more with 1R. So it is not impossible to use one each channel, plus i don't think your tubes will feel starved with 105mA vs 100mA or even 95mA.
Thanks for the advice Salas and RollE2k, agreed that some breadboarding and pragmatic design should do the job.
It's OK, really. Proven on practice.
Yes, It's possible, but higher current demand lowers the dynamic resistance of the CCS and asks more voltage across (the compliance voltage).
Agree.