Wondering if anyone knew of a simple circuit to indicate the active DAC sync frequency with single LED's? I have seen one circuit that shows whether it is 96kHz or not, I think that was just an LED driven by a dedicated DAC pin IIRC. With the myriad of DAC and support chips out there I was wondering if there was something with even more granularity, but not a full segment display?
in order to detect only one frequency you can use a pll such a 4046. Led will light on pll locked status detected. Pll will act as a sharp band pass filter.
see : https://www.ti.com/lit/an/scha002a/scha002a.pdf
In order to detect multiple frequency a f to V converter followed by 1 windows comparator per frequency to detect should be doable.
With a uc it’s easier, you setup a counter running on internal clock but gated by the signal you which to measure frequency. You get counter value on gate events then you re able to compute the signal frequency. But this doesn’t really fit your ’simple circuit’ criteria…
see : https://www.ti.com/lit/an/scha002a/scha002a.pdf
In order to detect multiple frequency a f to V converter followed by 1 windows comparator per frequency to detect should be doable.
With a uc it’s easier, you setup a counter running on internal clock but gated by the signal you which to measure frequency. You get counter value on gate events then you re able to compute the signal frequency. But this doesn’t really fit your ’simple circuit’ criteria…
Forgot to mention : the signal to measure is LRCK , also named WS, on I2S interface and it usually run at sampling frequency : 44.1k, 48k,….
You could try something like this - neither tried nor tested, so use at your own risk. It is very well possible that some of the resistors connected to the 74HC123's will need to be changed by an E12 step up or down.
You can extend it with more stages if you also want to distinguish between 44.1 kHz and 48 kHz or between 88.2 kHz and 96 kHz, but then you will definitely need trimmable resistors.
You can extend it with more stages if you also want to distinguish between 44.1 kHz and 48 kHz or between 88.2 kHz and 96 kHz, but then you will definitely need trimmable resistors.
There are "frequency counter crystal tester" kits based on PIC microcontrollers with an LED display. Source code is available; maybe it can be modified. Or just don't install or cover up the digits you don't need.
https://github.com/TheHWcave/PIC-freq.counter-modification
The most elegant microcontroller solution might be an Attiny85; those just have enough pins for input and a few output LEDs. They can be programmed in Arduino, and are available on convenient little modules if you search ebay for Digispark.
https://github.com/TheHWcave/PIC-freq.counter-modification
The most elegant microcontroller solution might be an Attiny85; those just have enough pins for input and a few output LEDs. They can be programmed in Arduino, and are available on convenient little modules if you search ebay for Digispark.
With phase-detectors like the ones inside 4046 PLL, the filtered output is proportional to the phase (not frequency) difference.
However, if the LRCLK is made to trigger a monoshot, the average output voltage would be proportional to the frequency deviation (vs. phase), which is what you want. You may then use a multi-window comparator to distinguish between the various sample-rates and light up LEDs.
I think this explains Marcel's circuit using the 74HC123.
However, if the LRCLK is made to trigger a monoshot, the average output voltage would be proportional to the frequency deviation (vs. phase), which is what you want. You may then use a multi-window comparator to distinguish between the various sample-rates and light up LEDs.
I think this explains Marcel's circuit using the 74HC123.
In this use case, PLL is not used to track phase. it is used to provide a lock signal. A PLL has a locking frequency range, if you set the center of this range to frequency you want to detect (lets say 44,1kHz) and the lock range small enough, PLL will lock around 44.1k but not on 48Khz or more. This is kind of frequency discriminator : what's OP asked for.
A lock signal is easily build around a 4046, this is described in §4.4 of the appnote : https://www.ti.com/lit/an/scha002a/scha002a.pdf
A lock signal is easily build around a 4046, this is described in §4.4 of the appnote : https://www.ti.com/lit/an/scha002a/scha002a.pdf
No offence, but if that's the case, then the OP would need one PLL chip per sampling frequency, since the output is digital (yes/no). I think Marcel's circuit would be easier to get right, as it directly counts the number of monoshot pulses to give an output voltage proportional to the frequency.
Another advantage I see here is that Marcel's circuit gives an analogue output, that can represent literally any frequency if the meter / readout /gauge is calibrated properly.
Another advantage I see here is that Marcel's circuit gives an analogue output, that can represent literally any frequency if the meter / readout /gauge is calibrated properly.
With some dac chips (ESS) the incoming sample rate can be deduced from the control registers. A spare GPIO pin on the dac chip can used to light up an LED. Since there is usually an MCU anyway, the incremental cost is almost free.
EDIT: Also, if using a USB board then the sample rate can be read from the F0 - F3 status pins. In addition, if using a SPDIF receiver such as AK4118, and if it is equipped with a low cost crystal, then it can detect the incoming sample rate.
EDIT: Also, if using a USB board then the sample rate can be read from the F0 - F3 status pins. In addition, if using a SPDIF receiver such as AK4118, and if it is equipped with a low cost crystal, then it can detect the incoming sample rate.
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You could also do that, but it is not exactly how my circuit works. My circuit uses one retriggerable monostable multivibrator per frequency threshold, and a kind of spike detector circuit consisting of two resistors, a diode, a capacitor and a Schmitt trigger after each monostable multivibrator.
If the frequency is higher than the reciprocal of the monostable multivibrator pulse width, the monostable multivibrator remains triggered, its Qnot output remains low continuously and the spike detector circuit turns its LED on.
If the frequency is lower, the Qnot output goes high periodically (or continuously if the frequency is 0) and the spike detector circuit turns its LED off.
You could also use a PLL and a bunch of window comparators, by the way. Make a PLL with a phase-frequency detector (PFD) and with a VCO with a wide tuning range, and connect the window comparators to the VCO tuning input.
Regarding the circuit of post #6, don't use Toshiba 74HC123's, because their pulse width is totally different from those of the Nexperia 74HC123 and Texas Instruments CD74HC123. I used the Philips (now Nexperia) datasheet when determining the values of the timing resistors.
The 123s and the post filter made me think that it was some variation of what I said. Sorry for not paying enough attention.
Since the capture range / lock range of the PFD-based PLL is dependent on the filter time constant, I really doubt if a PLL with (say) a 96kHz centre frequency would have sufficient capture range to lock onto 32kHz and 192kHz in the same way. The idea however is elegant.MarcelvdG said:
Sorry, I just checked now, with a PFD, the lock range is independent of the filter. The above method could actually work.
You could use it for DoP, but not for raw DSD, not directly anyway.
For raw DSD, you would have to monitor the bit clock and use much shorter pulse widths, so short that a plain old 74HC123 gets very inaccurate, if it works at all.
One way to fix that, would be to put a counter/frequency divider between the bit clock and the monostable multivibrators. The simplest option would be an asynchronous binary counter IC. You would have to make sure that the clock subharmonics generated by the counter don't end up on the DAC clock or voltage reference.
For raw DSD, you would have to monitor the bit clock and use much shorter pulse widths, so short that a plain old 74HC123 gets very inaccurate, if it works at all.
One way to fix that, would be to put a counter/frequency divider between the bit clock and the monostable multivibrators. The simplest option would be an asynchronous binary counter IC. You would have to make sure that the clock subharmonics generated by the counter don't end up on the DAC clock or voltage reference.
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It seems a lot complicate for a newbie like me. So I will continue reading at the player what kind of DSD is, thanks.