Take a look what PMA, who you often quote, has to say about measurements:
https://www.audiosciencereview.com/...ents-everything-or-nothing.29062/post-1670946
Measurements in general are essential, no argument there. However misuse and or misinterpretation of FFTs is probably not what PMA means by competence.
@Markw4 I appreciate your contributions to this community. My posts can get lengthy precisely because I want to take care to address all input carefully. My questions and considerations to you should be in there. I do not have nor want any beef with you, in the contrary. Sharing different perspectives is one joy of the hobby to me.
I did say that I know and agree that running clocks continuously stabilizes them, and that I have chosen differently for my use case. I might as well have designed it with just a 22.5792 MHz clock. Having just one running reduces crosstalk and emanated power supply noise. So while I know and understand why you would do it differently, this is the oscillator switching topology that I will be keeping (although in an upcoming revision I did improve switching by changing the NOT gate into a 74LVC1G39 decoder).
That said I am going back and forth between clocks. That SC-PURE that IanCanada is offering looks good and keeps the oscillator running even when the output is disabled. I like those RFX OCXOs as well but they are risicoulously expensive. Which brings me to the NDKs which seem excellent at a fraction of the price of even the Crysteks. I will sign up to the SC-PURE group buy and see where those prices will end up.
Having some spare 0805 and 0603 pads for experimentation is indeed something useful in the PCB design.
The same applies to pi filters because you can just short the pad to the bead with a 0R resistor and keep the capacitor pads open to experiment.
I do think it is kind of hard to argue against pi filters or more generally CLC filters as a well-known and regarded mechanism to reduce power supply noise. Yes I know and understand magnetic hysteresis. So how should I approach the article by Purifi? That’s in the context of unwanted changes to an AC waveform as an output of a switching amplifier. Here we are considering attenuating DC power supply ripple as an output of a linear regulator.
But we digress, as this should be a thread about PCM2DSD integration. With pads available to short or populate, anyone can do what he or she wants.
I did say that I know and agree that running clocks continuously stabilizes them, and that I have chosen differently for my use case. I might as well have designed it with just a 22.5792 MHz clock. Having just one running reduces crosstalk and emanated power supply noise. So while I know and understand why you would do it differently, this is the oscillator switching topology that I will be keeping (although in an upcoming revision I did improve switching by changing the NOT gate into a 74LVC1G39 decoder).
That said I am going back and forth between clocks. That SC-PURE that IanCanada is offering looks good and keeps the oscillator running even when the output is disabled. I like those RFX OCXOs as well but they are risicoulously expensive. Which brings me to the NDKs which seem excellent at a fraction of the price of even the Crysteks. I will sign up to the SC-PURE group buy and see where those prices will end up.
Having some spare 0805 and 0603 pads for experimentation is indeed something useful in the PCB design.
The same applies to pi filters because you can just short the pad to the bead with a 0R resistor and keep the capacitor pads open to experiment.
I do think it is kind of hard to argue against pi filters or more generally CLC filters as a well-known and regarded mechanism to reduce power supply noise. Yes I know and understand magnetic hysteresis. So how should I approach the article by Purifi? That’s in the context of unwanted changes to an AC waveform as an output of a switching amplifier. Here we are considering attenuating DC power supply ripple as an output of a linear regulator.
But we digress, as this should be a thread about PCM2DSD integration. With pads available to short or populate, anyone can do what he or she wants.
True. But we did all sorts of testing here to see if it was a problem. It wasn't. Otherwise we would have fixed it.
Anyway, understood its you project and you can do what you want with it. Enjoy 🙂
Ah l I had not gotten that point. In that case I might as well go for the relay. Costs a few Euros more but for a DIY project that’s water under the bridge.
Another thing we did was have multiple regulators on the board. I used pin headers with jumpers, but pads could work fine to try different load sharing on different regulators. For one project, 3 regulators was found to be sufficient. Wasn't obvious at the outset it would turn out that way though. Also, loading regulators with resistors for tests of adjusting pass transistor current and thus loop gain may require some TH pads. This of course is for people willing to try some experimental R&D. Not everyone's cup of tea.
EDIT: relays I measured only had .2pf of capacitance between open contacts. Not too much of a problem with 22/25Mhz clocks as it turned out, even with the edge harmonics.
EDIT: relays I measured only had .2pf of capacitance between open contacts. Not too much of a problem with 22/25Mhz clocks as it turned out, even with the edge harmonics.
Interesting project indeed! If anyone has a spare pcb for sale, I would like to buy it. Preferably from Europe. Please PM then.
eziitis,
Do you have a JTAG programmer to load the FPGA firmware?
Also, the voltage regulators have been in and out of stock at distributors. Same for the FPGA in the version called out in the BOM. There are some alternate part numbers for some of those things, if needed.
Last thing I would mention is that for best results the FPGA output should probably be reclocked, and maybe galvanically isolated. The version 3 firmware can sound very good, especially if used with hi-res PCM. But best sound is if everything else is in good shape too.
Just telling you all this because a board is not the only thing that can involve some time and money.
If none of that stuff is a problem, getting a board should be the easy part. Please PM if you can't find one in Europe.
Do you have a JTAG programmer to load the FPGA firmware?
Also, the voltage regulators have been in and out of stock at distributors. Same for the FPGA in the version called out in the BOM. There are some alternate part numbers for some of those things, if needed.
Last thing I would mention is that for best results the FPGA output should probably be reclocked, and maybe galvanically isolated. The version 3 firmware can sound very good, especially if used with hi-res PCM. But best sound is if everything else is in good shape too.
Just telling you all this because a board is not the only thing that can involve some time and money.
If none of that stuff is a problem, getting a board should be the easy part. Please PM if you can't find one in Europe.
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On vacation so plenty of time to think 🙂 and have also thought about galvanic isolation between the FPGA and output device. For sure it’s a good idea to keep that FPGA noise out.
I’m thinking two options:
1 - simple but effective: just a set of separate flip flops. This will not just reclock but also buffer, and in doing so effectively decouple FPGA noise.
As an aside, in my last posted schematic I had three flip flops cascaded from dual gates. Seems better to just use a single gate with no cascading. Reclocking is synchronous so should not be metastable, and this will have lower additive jitter.
2 - galvanic isolation: using a series of separate isolator ICs. Issue is how to deal with MCLK. Using three isolators for DSDCLK, DSDL and DSDR will defeat the galvanic isolation when you still need to feed MCLK and reference it to the dirty GND. But isolate MCLK and you will lose all virtues of a low phase noise MCLK. I think the best isolators have total jitter figures like 70ns ps?
You could add a jitter cleaner on the isolated side. So a PLL. Doesn’t have to be half bad, and still synchronized, but not a precise clock copy, just a clock reconstructed.
So what to do? My guts say option 1 but would be interested in experimenting with 2 too.
Clearly I’m interested in integrating this board with devices besides just DSC. Let me know if you want this going to a separate thread.
I’m thinking two options:
1 - simple but effective: just a set of separate flip flops. This will not just reclock but also buffer, and in doing so effectively decouple FPGA noise.
As an aside, in my last posted schematic I had three flip flops cascaded from dual gates. Seems better to just use a single gate with no cascading. Reclocking is synchronous so should not be metastable, and this will have lower additive jitter.
2 - galvanic isolation: using a series of separate isolator ICs. Issue is how to deal with MCLK. Using three isolators for DSDCLK, DSDL and DSDR will defeat the galvanic isolation when you still need to feed MCLK and reference it to the dirty GND. But isolate MCLK and you will lose all virtues of a low phase noise MCLK. I think the best isolators have total jitter figures like 70
You could add a jitter cleaner on the isolated side. So a PLL. Doesn’t have to be half bad, and still synchronized, but not a precise clock copy, just a clock reconstructed.
So what to do? My guts say option 1 but would be interested in experimenting with 2 too.
Clearly I’m interested in integrating this board with devices besides just DSC. Let me know if you want this going to a separate thread.
Hmm, the ADN465x isolated LVDS drivers are stated to have 387 fs rms of jitter 100 Hz - 100 kHz for a 10 MHz carrier. That’s pretty good! Not sure how this relates to the 70 ps of total jitter though?
MCLKs have to be on the dac side of any isolation barriers. A copy of MCLK can be sent over an isolator back to the USB board and or DSD converter. Jitter doesn't matter at that point, only at the dac.
Regarding dac phase noise for DSD dacs, they tend to be more sensitive to phase noise than PCM dacs so its not uncommon to see phase noise measurements down to .1Hz offset. That said, some people seem to feel that 1Hz to 10Hz is the critical band for close in phase noise in terms of reproducing LF transient envelopes. Lower offsets than that may or may not have something to do with imaging.
Regarding dac phase noise for DSD dacs, they tend to be more sensitive to phase noise than PCM dacs so its not uncommon to see phase noise measurements down to .1Hz offset. That said, some people seem to feel that 1Hz to 10Hz is the critical band for close in phase noise in terms of reproducing LF transient envelopes. Lower offsets than that may or may not have something to do with imaging.
I am thinking to experiment 1+2 (simultaneously).
1 is as you already said, but 2 is for the Amanero side, to isolate the noise coming from the USB host. Amanero should be set to work in slave mode, and it will receive the isolated "copy" of MCLK. So, the low phase noise MCLK remains on the DAC (and FPGA) side. I am still looking for a lower noise LDO, to replace the 1.2V 1117_type LDO for FPGA Vcore.
Both 1 and 2 are useful for DSD although Delta-Sigma dacs may work well with only option 2 provided they have clean MCK. Option 1 alone does not make much sense. And as Markw4 said DACs require clean MCK but it can be sent to USB/converter board through isolator provided option 1 is used after the isolator on the generated signals. Delta-Sigma dacs need only option 2 for PCM if MCK is clean.
I've been listening to the updated PCM2DSD today - it's been reflashed with the recent firmware release (thanks @Cestrian ). I have to say that I honestly don't recall the sound with the previous firmware well enough to comment on whether I perceive a difference but, regardless, it does sound very good, if not, IMO, quite up there with HQ Player based playback.
Would like to mention that version 3 firmware has 4dB of PCM attenuation built-in to avoid intersample overs and such. It can still distort a little sometimes if the PCM input level is too high. Not so much a problem with hi-res PCM because it tends to be recorded with more headroom than 16-bit CD audio. For CD, especially for pop type music, its not uncommon for reconstructed peak levels to reach +1dBFS or even a little higher. In that case it may help to reduce a little bit of distortion on volume peaks if PCM level is dropped a few dB before going into PCM2DSD. It is not recommended to attenuate more than a few dB or SNR/DNR may be made worse. Mostly the distortion issue has been most noticeable here with pop CD vocal harmonies that can sound a little too bright and gritty, instead of nice, pleasant. Using PlayPcmWin its possible to turn down PCM playback a little using a dropdown menu. I have it set to -4dB at the moment.
It is possible to install
https://www.mouser.sk/ProductDetail/Xilinx/XC6SLX9-2TQG144C?qs=rrS6PyfT74cKOj/X/YJ9TA==
for PCM2DSD , or where to buy the right FPGA for this PCB?
https://www.mouser.sk/ProductDetail/Xilinx/XC6SLX9-2TQG144C?qs=rrS6PyfT74cKOj/X/YJ9TA==
for PCM2DSD , or where to buy the right FPGA for this PCB?
Hello,
A question that is not related to current discussion. Do you know the processing time of the modulator ? I am using it to listen to music right now, so it's not a problem, but if i want to use it to watch some concert, i need to to play with the audio shift function. Not hard to find an approximation of course, just want to know if there is a precise data for this.
A question that is not related to current discussion. Do you know the processing time of the modulator ? I am using it to listen to music right now, so it's not a problem, but if i want to use it to watch some concert, i need to to play with the audio shift function. Not hard to find an approximation of course, just want to know if there is a precise data for this.