Yeah, it's great if you have wired connection available, it's what I prefer but not always convenient.
Then this is the wrong thread for you. Conversion to DSD is done in the FPGA, so the player software doesn't need to.
IME simple DSD converter is worth the time and money, at least if you know how to use it correctly. Among other things that means you clean up and reclock the I2S outputs before sending them to the dac. You should also use good master clocks in a good implementation. Avoid radiated and conducted RFI/EMI, avoid ground loops, use good, clean linear voltage regulators, etc.
I'm using the FPGA converter and so is Andrea Mori. Maybe somebody just needs to design the rest of the stuff you need to get the best out of it and post it as a diy project?
I'm using the FPGA converter and so is Andrea Mori. Maybe somebody just needs to design the rest of the stuff you need to get the best out of it and post it as a diy project?
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If anyone would be interested in possibly taking that on but would first like to discuss implementation ideas, please feel free to PM.
Used master clocks, very good regulated PSUs, no matter sounds very bad...
Andrea Mori stuff is for rich!!!
Did you reclock with D-flip flops on a 4-layer PCB with a ground plane? Do you have a pic of what you did?
Because that's basically what happens in a USB board. The I2S is clocked out by MCLK, usually through a CPLD. A CPLD may be better for that as compared to an FPGA. To reclock the I2S bus after it passes through an FPGA can help. Another potential problem is that both USB boards and FPGA boards can produce radiated EMI/RFI. If the radiated emissions are allowed to couple into the dac, that can sound bad. IOW, there are potential pitfalls for the unwary. Loose wires hanging the air, one shared ground for all the I2S signals, and other stuff like that is likely to produce impaired performance.
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Oh, Chronus. I tried one of those. One of the worst I tried. Helped some to put it in a steel shielding enclosure. Eventually I designed my own solution. Final stage voltage regulation needs to be on the same ground plane as the clocks. IIRC Chronus has an ADM7150 (or similar) next to the clocks. Again IIRC the clocks outputs are routed through an analog switch, then some of the MCLK signal is buffered by a Potato Semi logic chip. Some of the other MCLK loads are directly connected to the clocks without proper buffering. Yet again IIRC everything on the board is powered by the one ADM7150, which as a result makes the clock power dirty.
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