DIYed discrete DSM DACs usually consist of analog FIR architecture, where several DACs are paralleled(16 or 32). Their transitions simultaneously occur. The max transitions(switchings) are 16 if your DAC has 16DACs(taps). The minimum is probably 3. The max is around zero(0101010101010101), while the min is at max amplitude(111101111101110). Both cases have switching noise, but the different numbers of transitions have different noise amplitude. Even if the sampling frequency is far above the audio band, the noise amplitude is synchronous with the output frequency. That's why the switching noise caused by 64OSR or 128OSR ends up THD in the audio band. If your DAC is monolithic, like ak4499, the switching noise is far less than a discrete one. A DIYed discrete DAC has a relatively large switching noise. One of the solutions to decrease the switching noise is to use a low OSR. But a low OSR means less noise-shaping. I would use 256OSR if I had a low-switching noise DAC.
I can't believe 17th-order DSM exists in the real world. Even 8th order is huge enough to require 48-bit calculation. If 17th-order exists on the planet, it may be in the Jurassic world, IMO. 17th-order probably needs 112-bit calculation. What you can get from 17th-order is an enormous waste of resources and incredible out-of-band noise. A possible theoretical solution means something other than a cool one.
I can't believe 17th-order DSM exists in the real world. Even 8th order is huge enough to require 48-bit calculation. If 17th-order exists on the planet, it may be in the Jurassic world, IMO. 17th-order probably needs 112-bit calculation. What you can get from 17th-order is an enormous waste of resources and incredible out-of-band noise. A possible theoretical solution means something other than a cool one.
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@xx3stksm : Hi ... Just a quick question slightly digressing on the subject of this thread, though ... Might there be an accessible (i.e. not too tricky) way of making your FPGA & transistor DSD DAC without the use of an FPGA? Not a programmer myself (and unfortunately not with enough time to learn programming to the extent that I assume is necessary) it would be very interesting if this was possible ...
Cheers, Jesper
Cheers, Jesper
The most important thing to make a discrete DSM DAC is to minimize switching skew between taps, IMO. FPGA is the best device to decrease the skew because it has an internal PLL with a fine phase adjustment function. A discrete logic IC has a different low-to-high and high-to-low delay. It takes work to compensate for the difference; unmatched switching time results in disappointed performance. But even FPGA will be obsolete, especially DIY-friendly spartan 6. Unfortunately, a discrete DSM DAC with FPGA would be an old-school design.
@xx3stksm: Thanks once more for your feedback. Your comments about discrete logic skews & delays etc. make sense - I reckon it can be quite challenging to correct for this in a discrete circuitry (if at all possible).
And then I am a bit puzzled by this comment of yours:
But isn't this what you are doing? I.e. using an FPGA to make a discrete DSM DAC? Or maybe I am missing something here (terminology maybe)?
Cheers, Jesper
And then I am a bit puzzled by this comment of yours:
But isn't this what you are doing? I.e. using an FPGA to make a discrete DSM DAC? Or maybe I am missing something here (terminology maybe)?
Cheers, Jesper
I used to design and manufacture video products. I had several experiences with out-of-stock problems. So, I usually buy some critical parts before designing a PCB to be able to populate my PCBs. But the out-of-stock problem with FPGA was way beyond my imagination. I'm sure AMD said they would supply old FPGAs like spartan6 for several years. But after covid19 crisis, they broke the promise. Spartan6 in BGA(BGA is mandatory to drive a differential load) is de facto obsolete and will not be available in the future. Without ISE14.7 devices, hacking FPGA is almost impossible. There is no way to design an excellent discrete DSM DAC, unfortunately. FPGA with ak4499EX is possible but not cool for me. FPGA with some analog section could be an alternative. It's challenging.
@xx3stksm do you have any opinion/advice about other FPGA manufacturer?
I have made 24 taps version of your discrete DSM DAc, using IntelAltera Cyclone IV chip, and the first results are very promising - no measurements yet, but a few hours of listening music. This is the first prototype, I already found some small PCB routing mistakes, but it still sounds good to me.
I have made 24 taps version of your discrete DSM DAc, using IntelAltera Cyclone IV chip, and the first results are very promising - no measurements yet, but a few hours of listening music. This is the first prototype, I already found some small PCB routing mistakes, but it still sounds good to me.
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@Thorp,As far as I know, Xilinx and Altera are two giants in the FPGA world, though big companies purchased both. LCSC has some xc6slx9 at a reasonable price. I wonder if it's real or fake.
https://www.lcsc.com/search?q=xc6slx9
Your attached pic is fantastic. Each driving trace looks the same length. But is it possible to convert the code for xc6slx to Cyclone?
https://www.lcsc.com/search?q=xc6slx9
Your attached pic is fantastic. Each driving trace looks the same length. But is it possible to convert the code for xc6slx to Cyclone?
Regarding AK4499 or AK4499EX, IMHO dac design can still have its challenges in the analog domain. Standard IC voltage regulators, standard 3-opamp output stages, and so forth are IME not the best way to get great SQ out of a dac chip. Those things measure well, of course. Hopefully more and more people are starting to understand measured figures of merit do not exactly correlate with how humans perceive sound. Approximately, yes. Exactly, no. There is no textbook on how to do dac analog audio design best in terms of human perception, at least not yet.
Thanks! Yes, they are the same length, all 48 taps differential traces (the other 24 taps are on the bottom side of PCB).
I had no code for spartan to convert, I even don't know if it is possible, so I had to make it from scratch for cyclone.
Don't know that the term 'the human perception' is meaningful other than in usage such as in the following research title: https://journals.plos.org/plosbiology/article?id=10.1371/journal.pbio.0020146 Other than that, there does seem to be something along the lines of, say, for example, 'Thresholds of Audibility' where one property of average human perception can be estimated.
Moreover, human perception can be evaluated in a number of different ways as summarized in Table 1, page 6, of the attached document. Many of the methods do not rely on electronic instruments to take 'measurements.'
Great
. Only some people can make it from scratch. Can you convert your code to xc6slx9?I am affraid that would be a big challangeGreat
, as I am still a beginer in the FPGA field. EP4CE40 is "easy" to work with, because it is huge compared to XC6SLX9!SLX16 seems to be a better intermediate step for me.
At first I should reduce it from 32 bit to 24 bit, I supose.
At the second step I probably should re-design or reduce the interpolation FIR filters chain.
At the third step I should learn more about CSD or other methods to save multipliers and/or other resources.
At the fourth step, I should find some FPGA-specific optimization methods, maybe to find another dithering method for SD modulator, etc.
And so on...
I love to learn, but this is a hobby, and free time for hobbies is my biggest challange.
Anyway, my current project is DSM based dac for RPi, based on XC6SLX16. Still working for a prototype PCB (I have no eval/learning board, but only 2 pcs. of SLX16 chip).
Not sure what you mean. I will attach a quote that explains about DoP verses Native DSD as it relates to most USB boards:
"DoP DSD and native DSD are the ways audio is transferred between the used audio player and XMOS processor on the USB board, i.e. the player may be set to DoP - then this means that information between PC/USB host and XMOS processor is coded DoP DSD, i.e. DSD in PCM frame; or if the player is set to DSD native, then the information between PC/USB host and XMOS processor is not coded and it's DSD native. But on output of the XMOS processor id always DSD native."
Regarding playing DSD files from Windows, IIUC only ASIO drivers support Native DSD. If WASAPI Exclusive Mode drivers are used then DoP format is required. As described above, at the USB board DoP is usually converted back to Native DSD before being sent out on the I2S bus to the dac chip.
Yes, it's challenging to install a 2-channel DSM into xc6slx9. My first attempt was xc6slx25. The most crucial one is not the number of multipliers but fast carry adders, IMO. The multipliers are easy to count, but fast carry adders are unpredictable. You can't know the result until Place & route finishes. 80% usage is the max, in my experience. My strategy is time-multiplexing to make the best of it. Two times multiplexing is easy to implement. Even four times is possible with a 100MHz clock.I am affraid that would be a big challange
Another one is a fixed-coefficient multiplier; some of the multiplication for DSM is done between fixed coefficient and variable one. Minimizing resources is old-school technology because you have a large FPGA at a low cost. But for a DIYer, the lost technology is still interesting.
You could see that very clearly on the Trenz Electronic website. Before COVID-19, they had dozens to hundreds of each of their types of FPGA modules in stock, in 2020-2021 more and more modules went out of stock with estimated lead times of many months, and nowadays they have almost nothing in stock and don't specify lead times anymore.