Something else which has not found sufficient consideration in this thread (John Curl just quickly touched it): noise contribution from the input AC-coupling network.
I have little idea how ikoflexer's current implementation looks like but I recall one schematic with something like a 1 uF/30k network. Such will contribute about 120 pV/sqrt(Hz) at 1 kHz--calculated by dividing the thermal noise of the resistor by the low-pass attenuator ratio between resistor and capacitor at this frequency.
By doubling the resistor value the thermal noise increases by 3 dB but the attenuation goes up by 6 dB; hence overall (pass band) noise contribution is lower with high resistance values. With film capacitors and JFETs I'd not use anything less than 1M, preferably 10M. The later value still gives 650 pV/sqrt(Hz) at 10 Hz so perhaps it might be wise to use a 2.2 uF cap for entirely negligible contribution within the frequency band of interest.
Samuel
I have little idea how ikoflexer's current implementation looks like but I recall one schematic with something like a 1 uF/30k network. Such will contribute about 120 pV/sqrt(Hz) at 1 kHz--calculated by dividing the thermal noise of the resistor by the low-pass attenuator ratio between resistor and capacitor at this frequency.
By doubling the resistor value the thermal noise increases by 3 dB but the attenuation goes up by 6 dB; hence overall (pass band) noise contribution is lower with high resistance values. With film capacitors and JFETs I'd not use anything less than 1M, preferably 10M. The later value still gives 650 pV/sqrt(Hz) at 10 Hz so perhaps it might be wise to use a 2.2 uF cap for entirely negligible contribution within the frequency band of interest.
Samuel
no, Rg is added for formal reasons, as the voltage steered current source is noiseless and the FETs noise is modelled by a resistor, being 2/(3gm) and its accompanied voltage source.
As for the rms adding, you're right and I'm feeling pretty ashamed about it.😱
regards
Welcome back! 🙂 I had a few days off from diy too, during which I scored a painful farmer's tan and a 4Kg flathead catfish.
On topic again: the current implementation has a 10uF input film cap with a 200K gate resistor. The signal source resistance is in parallel with Rg and the noise of this parallel combination gets amplified by the voltage gain, just like the noise of Rs and the intrinsic jfet noise Req do. So the output noise would be:
eno = sqrt(4 k T(Rsrc Rg/(Rsrc + Rg) + Req + Rs) Av + 4 k T Rd)
and
eni = eno / Av
wheer Rsrc is the signal source resistance, Rg is the external gate resistor, and Req is 2/(3 gm).
Juergen, don't worry, I make many more mistakes than you. I see now that in your notation Rg is the intrinsic jfet resistance. Then I agree with the figure you drew, but it would be nice to use different notation for intrinsic jfet resistances and for external resistances.
I used a small r, instead of a large R in the figure to show the different nature of rg.
regards
regards
I've done some more research in second stage noise contribution. I'm considering the basic topology which has found most attention in this thread; a common-source first stage with resistive load, followed by an inverting opamp integrator and global feedback to the source of the input transistor. For the time being we assume that the DC biasing (of whatever sort) has negligible noise contribution.
I'm interested in chosing the optimum drain current for the input transistors. Basically their voltage noise decreases with increasing drain current, however (as I've tried to explain earlier in this thread) due to their transconductance growing with the square-root of (and not in proportion to) drain current drain resistor and second stage noise contribution increases. That is if we keep the voltage across the drain resistor constant, i.e. the drain resistor value is chosen inversely proportional to drain current.
Here's a Matlab file which calculates the individual noise contributions: noise_vs_Id.m
JFET transconductance and JFET voltage noise as well as opamp current and voltage noise are entered as actual measurement data and not derived from potentially inaccurate theoretical models. Here's the result for 8 paralleled 2SK170 transistors and a drain resistor voltage of 5 V (the Matlab file however has been kept flexible so you can easy alter the parameters for other configurations): individual_contributions.png and total_noise.png
As we can see running the JFETs at Idss is clearly not the optimum bias point, particularly if the opamp has significant voltage noise. However even with the LT1028 50 mA has a slight advantage over 80 mA. If we consider that the lower bias point has many more advantages (as noted before, e.g. higher PSRR) I see few if any reasons to not explore this possibility.
I've also thought quite a bit about a suitable configuration with a CCS first stage load and I've come up with a promising solution by making a servo controlling the CCS. Making the CCS/servo noise contribution sufficiently low requires care, but it seems perfectly possible at low complexity. Gain accuracy and PSRR is simply much better, and the second stage opamp contribution becomes entirely negligible.
Samuel
I'm interested in chosing the optimum drain current for the input transistors. Basically their voltage noise decreases with increasing drain current, however (as I've tried to explain earlier in this thread) due to their transconductance growing with the square-root of (and not in proportion to) drain current drain resistor and second stage noise contribution increases. That is if we keep the voltage across the drain resistor constant, i.e. the drain resistor value is chosen inversely proportional to drain current.
Here's a Matlab file which calculates the individual noise contributions: noise_vs_Id.m
JFET transconductance and JFET voltage noise as well as opamp current and voltage noise are entered as actual measurement data and not derived from potentially inaccurate theoretical models. Here's the result for 8 paralleled 2SK170 transistors and a drain resistor voltage of 5 V (the Matlab file however has been kept flexible so you can easy alter the parameters for other configurations): individual_contributions.png and total_noise.png
As we can see running the JFETs at Idss is clearly not the optimum bias point, particularly if the opamp has significant voltage noise. However even with the LT1028 50 mA has a slight advantage over 80 mA. If we consider that the lower bias point has many more advantages (as noted before, e.g. higher PSRR) I see few if any reasons to not explore this possibility.
I've also thought quite a bit about a suitable configuration with a CCS first stage load and I've come up with a promising solution by making a servo controlling the CCS. Making the CCS/servo noise contribution sufficiently low requires care, but it seems perfectly possible at low complexity. Gain accuracy and PSRR is simply much better, and the second stage opamp contribution becomes entirely negligible.
Samuel
Samuel, I'm trying to understand better your results. In particular I don't understand how you're calculating the total noise contribution of the opamp:
NE5534 = sqrt((NE5534_En./Rd./gm).^2 + (NE5534_In./gm).^2);
I suppose the second term "NE5534_In./gm" is the opamp current noise times the impedance that it "sees" of the first stage? Which impedance would be the inverse of the total first stage transconductance?
The first term "NE5534_En./Rd./gm": the opamp noise divided by first stage simplified expression of gain?
It seems to be an over-simplification of the analysis of a trans-impedance amplifier. Please don't get upset, I look at this with my very limited knowledge, but this is what this looks like to me.
I looked for instance at the Burr-Brown app note and the noise analysis of the trans-impedance amplifier is quite different. For instance the opamp feedback resistor seems to be quite important in the analysis.
http://www.ece.umd.edu/class/enee417.S2007/handout/noise_analysis_of_fet_transimpedance_amp.pdf
This being said, I'm willing to try a lower bias point and then just measure the noise. Theory aside, if the noise is lower than what I obtained when using higher Id then I have no reason not to accept it. Do you happen to have a schematic that has proper biasing of the jfets and that runs at low Id? My attempts to come up with something ended up in failure. Any advice you might have could help.
Also, a bunch of bf862 just arrived, so they'll get used in the next version.
Are you going to post your ideas about the CCS load + servo controlling the CCS?
NE5534 = sqrt((NE5534_En./Rd./gm).^2 + (NE5534_In./gm).^2);
I suppose the second term "NE5534_In./gm" is the opamp current noise times the impedance that it "sees" of the first stage? Which impedance would be the inverse of the total first stage transconductance?
The first term "NE5534_En./Rd./gm": the opamp noise divided by first stage simplified expression of gain?
It seems to be an over-simplification of the analysis of a trans-impedance amplifier. Please don't get upset, I look at this with my very limited knowledge, but this is what this looks like to me.
I looked for instance at the Burr-Brown app note and the noise analysis of the trans-impedance amplifier is quite different. For instance the opamp feedback resistor seems to be quite important in the analysis.
http://www.ece.umd.edu/class/enee417.S2007/handout/noise_analysis_of_fet_transimpedance_amp.pdf
This being said, I'm willing to try a lower bias point and then just measure the noise. Theory aside, if the noise is lower than what I obtained when using higher Id then I have no reason not to accept it. Do you happen to have a schematic that has proper biasing of the jfets and that runs at low Id? My attempts to come up with something ended up in failure. Any advice you might have could help.
Also, a bunch of bf862 just arrived, so they'll get used in the next version.
Are you going to post your ideas about the CCS load + servo controlling the CCS?
Samuel's plots remind me of the rising of grunge in my phono FFTs left hand below JFETs corner frequency. The more I use the less the hiss but starker the grunge rise. Maybe 4 and just a bit degenerated with 4R7 each is a good compromise. I use over 1k Rdrain and over 40V B+.
If anything it might point out that the trans-impedance scenario isn't how the lowest noise can be achieved. The plot for the jfets individually does continue to decrease with higher transconductance (Id). Only when the opamp is added, it makes the total noise go up at higher Id, in Samuel's calculations.
Its a system thing. I guess we must shoot for the net total all things used catered for and balanced.
I agree, for sure. The end result is definitely the noise of the total device. I can't shake two lingering doubts. One is, with all due respect, the correctness of Samuel's analysis; the other is the fact that if correct, his analysis would apply, I think only to the trans-impedance topology. In other words, if the noise of the first stage decreases with increasing Id, then there might be some way of taking advantage of that.
However I don't want to diminish the importance of the other advantages which might be significant, when running lower Id.
However I don't want to diminish the importance of the other advantages which might be significant, when running lower Id.
There are two ways to look at it; the more intuitive (but less correct) one is to sum voltage noise contributions at the drain of the input JFET. The contribution of the opamp voltage noise is then simply referred to the input by dividing it through first stage gain (gm*Rd), hence En/(Rd*gm) = En/Rd/gm. Opamp current noise flows through Rd (giving a voltage noise figure equal to In*Rd) and is then divided again by first stage gain, hence (In*Rd)/(Rd*gm) = In/gm.
However as pointed out earlier in this thread the drain of the input JFET is actually a current, not voltage, node. The voltage noise of the opamp modulates the voltage across the drain resistor, generating a current noise equal to En/Rd. This is then referred to the input by dividing it by input stage transconductance, resulting again in En/Rd/gm. Opamp current noise contribution is directly referred to the input by division through input stage transconductance, which gives again In/gm.
Why simplified? Note that I do correct gm in the Matlab script to include the effect of the feedback network.
I don't see anything different to the extent that the considered cases can be considered to be equal; e.g. there is simply no direct opamp feedback resistor in our case, hence one does not need to consider it. Of course any mathematical analysis is simplified to some extent, but I don't see any significant effect here. And in any case additional noise sources just make things worse, not better...
Sure, but first of all I'd like to ask you to show us a detailed schematic of your current implementation, including everything down to the last decoupling cap.
No and no. The first no is because it doesn't matter if the following opamp is inverting or not. As pointed out above in this post this simply converts the drain of the input JFETs from a voltage to current node. Resulting noise contribution is the same.
The second no is because the effect happens even with a noisless opamp--just look at the individual drain resistor contribution. The effect is less drastic but if you reduce the voltage across the drain resistor to < 2 V total noise will rise towards Idss.
The analysis of second stage noise contribution ain't trivial and I can't swear nothing slipped my mind. However I can give reference to the LT1028 IEEE paper where the authors use the very same method--and just BTW also found that (even with the much higher gm of the bipolar transistors) the second stage adds significant noise at least at low frequencies.
As far as I know Scott Wurcer has designed several JFET opamps of which at least one was optimised for low noise. Perhaps he can share some more insight here.
Samuel
Will do, asap. But for now I take back the request. I think I should sweat through this one myself.
Some more food for thought: the transconductance (gm) of a JFET is basically given by gm = -2/Vp*sqrt(Id*Idss); if we fix the DC voltage across the drain resistor (VRd) the value of the drain resistor (Rd) is given by Rd = VRd/Id. As the gain (A) of a common-source amplifier is given as A = gm*Rd we get A = -2/Vp*sqrt(Id*Idss)*VRd/Id.
It is very easy to see that the gain of the common-source amplifier *decreases* with increasing Id if VRd is kept constant. Hence it is intuitively clear that the voltage noise contribution of the following opamp will be more significant at high drain currents (a similiar argument might be made for PSRR which decreases with Id).
Here's a little Matlab program to plot this (shown Vp and Idss values are typical for a 2SK170):
It's easy to modify the code to incorporate a source degeneration resistor; its presence slightly accentuates the effect of decreasing gain at higher Ids because the degeneration effect is more significant for high transconductances.
Samuel
It is very easy to see that the gain of the common-source amplifier *decreases* with increasing Id if VRd is kept constant. Hence it is intuitively clear that the voltage noise contribution of the following opamp will be more significant at high drain currents (a similiar argument might be made for PSRR which decreases with Id).
Here's a little Matlab program to plot this (shown Vp and Idss values are typical for a 2SK170):
Code:
clear all
% JFET parameters
Idss = 10e-3;
Vp = -0.45;
% drain current
Id = logspace(log10(0.1e-3), log10(10e-3), 100);;
% transconductance
gm = -2/Vp*sqrt(Id*Idss);
% drain resistor
Rd = 5./Id;
semilogx(Id, Rd.*gm, 'black')It's easy to modify the code to incorporate a source degeneration resistor; its presence slightly accentuates the effect of decreasing gain at higher Ids because the degeneration effect is more significant for high transconductances.
Samuel
Samuel, I'm going to be very busy with family for two days, but will come back with comments after. Or course, everyone, please go ahead with the discussion.
Some hints on simulation of second stage noise contribution. To understand all the interactions we want to separate the opamp noise contribution from any other noise source and also split opamp voltage and current noise. This is most easily accomplished by modeling the opamp noise by the standard means of an AC voltage source in series with one opamp input and an AC current source from ground to the relevant input.
Consider this schematic: opamp_noise_sim.png
To keep things as simple as possible a large capacitor (C1) is used in the feedback network which allows us to skip the servo. Drain current is now set by the voltage across the drain resistor R1, i.e. by V1 and the positive supply.
U1 is an ideal opamp and IIn/VEn model its noise contribution. By setting these AC sources to IIn = In/A and VEn = En/A (where A = R2/(R2 + R3) represents the amplifier gain and In/En the noise specification of the intened opamp) the AC voltage at the node OUT conveniently represents the opamp noise contribution related to the input. Note that the two AC sources are correlated while real world opamp voltage and current noise are mostly uncorrelated; hence two simulation runs (with one or the other source disabled) and subsequent RMS-addition are needed.
It is perfectly feasible to extend this simple model with a servo; the basic second stage opamp contribution won't be changed by this, but the servo noise contribution can be modelled as well.
I've compared the simulation results with the basic formulas I've given above for about a dozen vastly different configurations (different feedback network impedances, different number of input JFETs, various drain currents and drain resistor values). They are in excellent agreement with each other. My formulas slightly underestimate opamp voltage noise and slightly overestimate opamp current noise. As the deviation is below 10% for any investigated case I've not studied things further but I presume that the cause for this are JFET output conductance effects.
Samuel
Consider this schematic: opamp_noise_sim.png
To keep things as simple as possible a large capacitor (C1) is used in the feedback network which allows us to skip the servo. Drain current is now set by the voltage across the drain resistor R1, i.e. by V1 and the positive supply.
U1 is an ideal opamp and IIn/VEn model its noise contribution. By setting these AC sources to IIn = In/A and VEn = En/A (where A = R2/(R2 + R3) represents the amplifier gain and In/En the noise specification of the intened opamp) the AC voltage at the node OUT conveniently represents the opamp noise contribution related to the input. Note that the two AC sources are correlated while real world opamp voltage and current noise are mostly uncorrelated; hence two simulation runs (with one or the other source disabled) and subsequent RMS-addition are needed.
It is perfectly feasible to extend this simple model with a servo; the basic second stage opamp contribution won't be changed by this, but the servo noise contribution can be modelled as well.
I've compared the simulation results with the basic formulas I've given above for about a dozen vastly different configurations (different feedback network impedances, different number of input JFETs, various drain currents and drain resistor values). They are in excellent agreement with each other. My formulas slightly underestimate opamp voltage noise and slightly overestimate opamp current noise. As the deviation is below 10% for any investigated case I've not studied things further but I presume that the cause for this are JFET output conductance effects.
Samuel
Just as a side note I'd like to add that many if not most more recent bipolar IC opamps use input bias current cancellation. Typical input bias current cancellation implementations cause common-mode current noise; if the opamp current noise is measured with equal source resistances at both inputs this common-mode current noise is cancelled out. However in this (i.e. the LNA) and most other application the impedances at the two inputs are vastly different and common-mode current noise must by RMS-added to the standard differential current noise; the later is often smaller in magnitude than the former so the effect is not at all subtle.
Many datasheets do not clearly state how current noise is measured, or they only show the result for balanced source impedances. The LT1028 is such a part; I've measured the actual figure for one sample, and the RMS-sum of differential and common-mode current noise is given in my Matlab file linked some posts back.
Samuel
Many datasheets do not clearly state how current noise is measured, or they only show the result for balanced source impedances. The LT1028 is such a part; I've measured the actual figure for one sample, and the RMS-sum of differential and common-mode current noise is given in my Matlab file linked some posts back.
Samuel
Samuel, it's my turn to get out of town for vacation, and am in the middle of getting prepared. I noticed you have your private messaging turned off and wanted to mention something to you privately. My email is ikoflexer at gmail.com
Cheers
Cheers
Hello All -
Most JFets are incredibly noisy below 100Hz because they a tiny devices. At 1Hz their gate noise-voltage (EINV) is in the uV region.
The lowest noise op-amp I am aware of is the MAXIM MAX4238 chopper op-amp. This part has an input voltage noise-density of about 100nV at 10Hz and it drops from there all the way down to 0.001Hz to about 25nV/Rt-hz. The MAX4238 is a CMOS chopper op amp. A close second to the 4238 in noise is the Linear Tech LTC1250 CMOS chopper which has about twice the noise.
Above about 10Hz - 100Hz, a low-noise JFet, such as the LS170, may reach about 1nV/Rt-Hz from say 10Hz - 100KHz.
The optimum preamp would be a hybrid containing a chopper op-amp and a JFet. There would be a crossover network to shift the output from the chopper to the Jfet at about 10 - 100Hz. The noise plot of such a hybrid amp would show less than 50nV/Rt-Hz of input voltage noise-density starting at DC and gradually dropping to 1nV/Rt-Hz between 10Hz and 100Hz.
Those attempting to use JFets in single-ended preamp topologies will never see the best distortion specs. The JFet must be embedded in a simple compound amplifier with a bipolar second stage or a chopper op-amp second stage, which feeds back to keep the JFet at approximately constant drain current for all signal levels. As long as the JFet is kept at near-constant drain-current, the inherent JFet nonlinearities will not present.
Cheers!
Most JFets are incredibly noisy below 100Hz because they a tiny devices. At 1Hz their gate noise-voltage (EINV) is in the uV region.
The lowest noise op-amp I am aware of is the MAXIM MAX4238 chopper op-amp. This part has an input voltage noise-density of about 100nV at 10Hz and it drops from there all the way down to 0.001Hz to about 25nV/Rt-hz. The MAX4238 is a CMOS chopper op amp. A close second to the 4238 in noise is the Linear Tech LTC1250 CMOS chopper which has about twice the noise.
Above about 10Hz - 100Hz, a low-noise JFet, such as the LS170, may reach about 1nV/Rt-Hz from say 10Hz - 100KHz.
The optimum preamp would be a hybrid containing a chopper op-amp and a JFet. There would be a crossover network to shift the output from the chopper to the Jfet at about 10 - 100Hz. The noise plot of such a hybrid amp would show less than 50nV/Rt-Hz of input voltage noise-density starting at DC and gradually dropping to 1nV/Rt-Hz between 10Hz and 100Hz.
Those attempting to use JFets in single-ended preamp topologies will never see the best distortion specs. The JFet must be embedded in a simple compound amplifier with a bipolar second stage or a chopper op-amp second stage, which feeds back to keep the JFet at approximately constant drain current for all signal levels. As long as the JFet is kept at near-constant drain-current, the inherent JFet nonlinearities will not present.
Cheers!
