The notch is not noise-less (notably not below the notch frequency) and the 30dB notch compensation in REW boosts apparant noise around the notch frequency even more.
Since the noise of the Cosmos ADC is really low, the noise penalty from the above could outweigh the noise benefit of the make-up gain of APU.
I'd check with zero signal and derive a noise compensation factor from that. One has to double check that the noise floor does not rise with applied signal, though.
I want to use 45M/49M output directly from a good OCXO based on 22M/24M input MCLK. Is there a simple way to detect and compare the input frequency is 22M or 24M!? Eg using 74HC7046 to compare phase and give Lock/Unlock status...
Nothing from your list has been implemented. What was done is:
1. The noise shaper used is 7-order Leapfrog with unity gain.
A loop filter was put in the feedback path, most of the integrators shows only noise-like content.
Only the content of the last stage resembling the input wave. It is a kind of error feedback architecture.
2. All coefficients are 1 bit wide. No multiplications. I found it empirically mostly by trial & error approach.
3. It has about 40kHz bandwidth at 256x sampling rate. Maximum modulation index about 3/4.
4. Master clock is 1024x.
5. The output bit pattern representing -1 was 0001, for +1 was 0111.
6. Dithering was rectangular 0.25 from feedback amplitude.
7. Maximum accumulator length - 28bits, no overload clipping or other means to avoid instability.
I didn’t care about fs/2 because of using 16-tap FIRDAC output. It is comb filter for sub-harmonics of the carrier.
I would say it is mediocre modulator optimized for minimal use of FPGA resources.
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Are you sure you didn't implement less intermodulation distortion than my DAC 😉 ? How did you implement your FIRDAC?
My FIRDAC also has a notch at fs/2. The low-level distortion would probably be far worse without it. Those -130 dBFS distortion peaks are what is left despite the notch, the practically pattern-independent reference current and a couple of other common sense measures.
My FIRDAC also has a notch at fs/2. The low-level distortion would probably be far worse without it. Those -130 dBFS distortion peaks are what is left despite the notch, the practically pattern-independent reference current and a couple of other common sense measures.
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Do you mean you want to lock a voltage-controlled crystal oscillator at twice the frequency to an incoming master clock at either 22.5792 MHz or 24.576 MHz? You could do that with two PLLs (one for each crystal oscillator) and see which one locks. You have to look out for crosstalk from the one that doesn't lock then.
I implemented each FIRDAC using 16 single gate flip-flops. Any equivalent of LVC1G74 will do well.
Each flip-flop has individual decoupling cap 1uF 0603 and distributed electrolithic caps totally about 800uF.
Reference was built on 6 directly biased P-N junctions of BJT transistors and buffered with very low noise OPAMP. Thermal stability was sacrificed for the sake of Vnoise. It shows about a quarter of micro volt rms in 20-20k.
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So, is everyone satisfied having seen one FFT?
If so, maybe we could move on to the question of, "how does it sound?"
I have people sending me PMs fairly frequently asking about dac recommendations. Pretty sure those folks would be interested to know about this dac.
Also recently did a brief review of a Soekris dac1221 at: https://www.superbestaudiofriends.o...cost-soekris-dac1221.14493/page-2#post-436588 Tried to make it overall good natured, yet honest about the shortcomings. Typically when we have audio devices here for listening evaluations the results are not public.
Thing is, many people do want some idea of how these things sound and not just how well they measure.
If so, maybe we could move on to the question of, "how does it sound?"
I have people sending me PMs fairly frequently asking about dac recommendations. Pretty sure those folks would be interested to know about this dac.
Also recently did a brief review of a Soekris dac1221 at: https://www.superbestaudiofriends.o...cost-soekris-dac1221.14493/page-2#post-436588 Tried to make it overall good natured, yet honest about the shortcomings. Typically when we have audio devices here for listening evaluations the results are not public.
Thing is, many people do want some idea of how these things sound and not just how well they measure.
There are six of them, actually, one in post #3834 and five in post #3837.
I guess ska's DAC is a variant of this one: https://www.diyaudio.com/community/threads/discrete-fpga-dac-project.407618/
Presumably it's similar but with a simpler digital sigma-delta modulator.
You are right, Marcel. I used the same hardware and got the same result with most primitive modulator.
I have tons of spectrums, measurements but they all are mostly the same as before.
Only very long FFT skirts are not impressive for a very simple reason, it’s price for using PLL and VCXOs.
The summary is that most of the sigma-delta science is a kind of pure academic sport.
Only one formula is important: k*b/(1+k*b), when k-> infinity.
I can’t distinguish sound of my last 3 versions of the DAC. The actual problem is not a modulator bat accurate implementation of the reconstruction filter.
I have tons of spectrums, measurements but they all are mostly the same as before.
Only very long FFT skirts are not impressive for a very simple reason, it’s price for using PLL and VCXOs.
The summary is that most of the sigma-delta science is a kind of pure academic sport.
Only one formula is important: k*b/(1+k*b), when k-> infinity.
I can’t distinguish sound of my last 3 versions of the DAC. The actual problem is not a modulator bat accurate implementation of the reconstruction filter.
I think you either have managed to keep intermodulation between the idle tones to at least a 10 dB lower level than in my DAC, or you have an offset in your modulator you don't know about. It's easy to make an offset unintendedly in a digital circuit: truncate a number and you have a -0.5 LSB offset, invert instead of negate a two's complement number and you have a -1 LSB offset.
Intermodulation distortion between idle tones around half the sample rate can be due to crosstalk from data to clock or data to the voltage reference, so it could be that your PCB layout is better than mine.
I couldn't agree with you less. It helped me a lot finding suitable coefficients and understanding and solving idle tone issues.
One thing that is unfortunate about the academic literature on sigma-delta modulators is the fact that almost no one dares to write explicitly that the noise transfer function synthesis method is based on a linearized model and a rule of thumb. Richard Schreier was quite clear about it during a lecture in Lausanne in 2001. I finally understood the method after that.
That's hardly surprising when they all work quite well.
What about the DC offset test? Send it DSD codes to produce some DC offsets and see what happens?
Also, what about multitone tests? The time domain waveform can be more complex than a simple sine wave, maybe a little closer to a transient stimulus.
Also, what about multitone tests? The time domain waveform can be more complex than a simple sine wave, maybe a little closer to a transient stimulus.
Marcel,
All this subtle things are clearly seen if you look at FFT of the output of the Verlog RTL simulation.
There is no room for guessing. Simulation results of the entire digital signal chain are available too.
I’d say that key to perfection is high loop gain.
I got quite frustrated, seeing that it is the end of exiting journey into digital audio DAC design.
There is nothing to do there anymore. At least for myself.
All this subtle things are clearly seen if you look at FFT of the output of the Verlog RTL simulation.
There is no room for guessing. Simulation results of the entire digital signal chain are available too.
I’d say that key to perfection is high loop gain.
I got quite frustrated, seeing that it is the end of exiting journey into digital audio DAC design.
There is nothing to do there anymore. At least for myself.
I assume you are referring to my remarks about offset, as second-order intermodulation, data-to-clock crosstalk and data-to-reference crosstalk are analogue imperfections that cannot be covered by digital simulations. I agree that digital offsets can be found by digital simulations if you look for them, of course.
OK, so did you check by simulation for your simplified sigma-delta modulator that on average 50 % of the output samples are one and 50 % are zero when the input signal is zero? Or is there any chance that it might, for example, be 49.8 % versus 50.2 %?
If there is no offset, then yours must have less intermodulation distortion than my DAC, or your dithering scheme works better than PJotr25's.
You could make it exciting again by coming up with a set of constraints that force you to use a worse DAC - require that it is single-ended, turn it into a digital class D amplifier, require the use of a double-layer instead of a four-layer board, whatever. The worse you make the DAC, the clearer you notice differences between the modulator algorithms.
