It is hard to not hear what we expect.
Without details on the Capacitors fitted and their replacements we are like eunuchs talking about sex, much opinion, zero data.
But I'd expect noise to be much lower in the final setup. And much reduced sensitivity to mechanical resonance in the audio band, which are likely the dominant effects (they are in coupling capacitors afaict).
Thor
True, but I have another listener I can use before I convene the group. He is quite accurate, in part because he doesn't care what I did. He just hears the sound as it is. For me it sometimes takes some time not to care if an experiment worked or not. Other times the outcome is obvious right away. I just don't bother telling you about failures.
Beyond that, we use a certain methodology to judge specific sounds and or sound stage spatial locations at specific points in some standard tracks we use. In addition I have live instruments here for direct comparison. We are NOT judging based on preference, although an opinion may be expressed on that too.
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Roughly, maybe.
Changing the subject a bit, regarding the use of C0G caps along with X7R, I have seen that combination used over many years. IME when used on clock circuitry and or Vref circuitry, for me personally, I was disappointed with the sonic results. Of course, the exact results must depend on the exact case, the exact values, layout, etc. That said, still in my own experience I was left with the opinion that it had been tried plenty of times and never sounded right to me for some uses.
In that state of art period, it was forum member @diyiggy who came along and shared a couple of SMD film bypass caps he found to work well with Crystek957 clocks. He had no particular standing as an expert, yet I was curious to try the caps he recommended. It was more or less like this:
Recommended: 0.22uf Rubycon MU in 805 size: 16MU224MZ22012
Economy: Cornell-Doublier 0.1uf, 805 size: FCA0805C104M-J2
Well, darn it if diyiggy didn't turn out to be right. (The caps I used to replace ceramics in the other dac were the "economy" version.) Still don't know exactly why those particular SMD film caps work so well in certain audio RF applications but not so much for baseband analog audio. However, they are worth a try in some cases; that would be my recommendation anyway. (And, yes, I know about self-resonance, etc. -- I would still try the caps anyway.)
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Did some more measurements of bypass cap ringing with active probing, including 10MΩ || 1.3pf, versus 1MΩ || 3pf. See some ringing up as high as ~700MHz. Amplitude and frequency is somewhat dependent on probe capacitance. Using a 1MΩ (instead of 10MΩ) probe attenuates ringing amplitude quite a bit. IOW, a lot of what is seen appears to be measurement artifacts in an insufficiently damped system.
This brings me to changing the subject a bit once again. What does anyone suppose using super low ESR bypass caps gets us other than a lot of ringing? Maybe that's much of the secret to the 805 size film caps. Maybe they give enough damping to produce a more or less stable system. Still thinking about it.
This brings me to changing the subject a bit once again. What does anyone suppose using super low ESR bypass caps gets us other than a lot of ringing? Maybe that's much of the secret to the 805 size film caps. Maybe they give enough damping to produce a more or less stable system. Still thinking about it.
Mark asked for my comment, so here it is:
Semantics
I wish people would stop using the word "noise" for just about anything. It gets almost meaningless like this.
Bit clock harmonics
Regarding bit clock harmonics on the supply and ground, they are in principle harmless, so I wouldn't worry about them.
Microphonics
Microphonics are a different matter. They can cause sidebands around the desired signal if there is enough vibration to cause significant microphonics. As demonstrated by bohrok2610 in the thread https://www.diyaudio.com/community/threads/phase-noise-in-ds-dacs.387862/post-7063038 , this is very well possible at frequencies below 10 Hz, even in a quiet room, when X5R capacitors are used for reference filtering.
Hence, I haven't used them for reference filtering, only for reference decoupling. This helps for frequencies below the loop bandwidth of the reference regulators and their decoupling, not for frequencies above that loop bandwidth. The loop bandwidth is 1/(2 π √(R17 C6 R16 (C19 + C21))) ≈ 277 Hz when the X5R capacitors have 80 % of their nominal capacitance at 5 V.
All in all, if there are strong enough vibrations at 277 Hz and above, non-microphonic decoupling capacitors could very well be an improvement. Of course that 277 Hz is not a hard limit, as the regulator is not a brick-wall filter; microphony at lower frequencies is suppressed to some extent, but there is no abrupt transition.
Data-related reference current and fancy decoupling schemes
The double-balancing with two SN74LV574A's cancels out data-dependence of the reference current, but it is inevitable that the cancellation is imperfect and that there is therefore some residual data-dependence of the reference current. Data-dependent reference current can cause intersymbol interference which can cause various issues, such as ultrasonic quantization noise intermodulating with itself and contributing to the audio noise floor, and intermodulation products between frequency-modulated idle tones around half the sample rate or around its odd harmonics. This latter effect caused the funny low-level distortion bohrok2610 measured, although it is unclear where the intermodulation occurs (the output filter seemed to be dominant at first, but this conclusion was later withdrawn, see pdf file attached to post #3265, https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/post-7686002 ).
The intersymbol interference via data-dependent reference current disturbing the reference voltage could be reduced by reducing the impedance of the reference supply. (In principle, one could also try to ensure that the reference supply settles before the next symbol comes. This is only applicable when the data-dependence only manifests itself some time before the next symbol starts, which is probably nonsense due to the interleaving between the even and odd parts of the FIRDAC.) As we are interested in frequencies far above 277 Hz, rather in the megahertz to dozens of megahertz range, the decoupling, PCB, SN74LV574A packages and bondwires and on-chip wiring determine the reference supply impedance.
It is very possible that all the fancy decoupling and six-layer recommendations of ThorstenL would help to achieve this, provided his recommendation to replace the SN74LV574A's with 16-bit bus flip-flops with multiple supply and ground pins such as the SN74ACT16374 is also followed up (otherwise the package and bondwire inductance will soon dominate). How much impact this has on the performance is unpredictable. Mind you, I'm assuming now that the timing requirements can be met with the SN74ACT16374, I haven't actually checked that.
The idea to place half the shift register ICs on the bottom reduces shielding between the data-handling circuitry and the rest, so I'm a bit wary of that. Besides, it doesn't seem useful with the 16 bit ICs.
One has to be careful with parallel resonances when several decoupling capacitors are connected in parallel. As long as the trace resistance plus the ESR of the capacitors is large compared to the square root of the ratio of the trace inductance to the series value of the decoupling capacitors, these resonances should be well-damped. It's therefore probably a non-issue when you either only use decoupling capacitors with really large values (my approach) or use supply planes as well as ground planes (ThorstenL's approach).
General
The DAC is good enough for me and has cost me enough money already, so I have no intention to test any of these potential improvements. If anyone else wants to, they are very welcome.
I do still want to make a discrete output filter, just for the hell of it, and try to see if an optimized version of my PWM8 modulator could be squeezed in a Spartan 6 LX9 FPGA.
Semantics
I wish people would stop using the word "noise" for just about anything. It gets almost meaningless like this.
Bit clock harmonics
Regarding bit clock harmonics on the supply and ground, they are in principle harmless, so I wouldn't worry about them.
Microphonics
Microphonics are a different matter. They can cause sidebands around the desired signal if there is enough vibration to cause significant microphonics. As demonstrated by bohrok2610 in the thread https://www.diyaudio.com/community/threads/phase-noise-in-ds-dacs.387862/post-7063038 , this is very well possible at frequencies below 10 Hz, even in a quiet room, when X5R capacitors are used for reference filtering.
Hence, I haven't used them for reference filtering, only for reference decoupling. This helps for frequencies below the loop bandwidth of the reference regulators and their decoupling, not for frequencies above that loop bandwidth. The loop bandwidth is 1/(2 π √(R17 C6 R16 (C19 + C21))) ≈ 277 Hz when the X5R capacitors have 80 % of their nominal capacitance at 5 V.
All in all, if there are strong enough vibrations at 277 Hz and above, non-microphonic decoupling capacitors could very well be an improvement. Of course that 277 Hz is not a hard limit, as the regulator is not a brick-wall filter; microphony at lower frequencies is suppressed to some extent, but there is no abrupt transition.
Data-related reference current and fancy decoupling schemes
The double-balancing with two SN74LV574A's cancels out data-dependence of the reference current, but it is inevitable that the cancellation is imperfect and that there is therefore some residual data-dependence of the reference current. Data-dependent reference current can cause intersymbol interference which can cause various issues, such as ultrasonic quantization noise intermodulating with itself and contributing to the audio noise floor, and intermodulation products between frequency-modulated idle tones around half the sample rate or around its odd harmonics. This latter effect caused the funny low-level distortion bohrok2610 measured, although it is unclear where the intermodulation occurs (the output filter seemed to be dominant at first, but this conclusion was later withdrawn, see pdf file attached to post #3265, https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/post-7686002 ).
The intersymbol interference via data-dependent reference current disturbing the reference voltage could be reduced by reducing the impedance of the reference supply. (In principle, one could also try to ensure that the reference supply settles before the next symbol comes. This is only applicable when the data-dependence only manifests itself some time before the next symbol starts, which is probably nonsense due to the interleaving between the even and odd parts of the FIRDAC.) As we are interested in frequencies far above 277 Hz, rather in the megahertz to dozens of megahertz range, the decoupling, PCB, SN74LV574A packages and bondwires and on-chip wiring determine the reference supply impedance.
It is very possible that all the fancy decoupling and six-layer recommendations of ThorstenL would help to achieve this, provided his recommendation to replace the SN74LV574A's with 16-bit bus flip-flops with multiple supply and ground pins such as the SN74ACT16374 is also followed up (otherwise the package and bondwire inductance will soon dominate). How much impact this has on the performance is unpredictable. Mind you, I'm assuming now that the timing requirements can be met with the SN74ACT16374, I haven't actually checked that.
The idea to place half the shift register ICs on the bottom reduces shielding between the data-handling circuitry and the rest, so I'm a bit wary of that. Besides, it doesn't seem useful with the 16 bit ICs.
One has to be careful with parallel resonances when several decoupling capacitors are connected in parallel. As long as the trace resistance plus the ESR of the capacitors is large compared to the square root of the ratio of the trace inductance to the series value of the decoupling capacitors, these resonances should be well-damped. It's therefore probably a non-issue when you either only use decoupling capacitors with really large values (my approach) or use supply planes as well as ground planes (ThorstenL's approach).
General
The DAC is good enough for me and has cost me enough money already, so I have no intention to test any of these potential improvements. If anyone else wants to, they are very welcome.
I do still want to make a discrete output filter, just for the hell of it, and try to see if an optimized version of my PWM8 modulator could be squeezed in a Spartan 6 LX9 FPGA.
Sounds very interesting the discrete output filter + your PWM8 modulator in a Spartan 6 LX9 FPGA, could be used for a noDac?
For the time being, I don't know yet if I am going to be able to redesign it such that it fits in an LX9. If I should manage to do so, you could use it for a noDac.
Ok.
Proposed semantics:
Noise: anything random/semi-random
LIM: any modulation of supply lines and thus switching points by logic switching
Clock Feedthrough: Clock and harmonics feeding through to a given circuit node
Data Feedthrough: Data and harmonics feeding through to a given circuit node.
Please lets be clear. Bitclock is incoming Signal, Shiftregister <> Bitclock.
I would worry about bit-clock, harmonics and non-harmonic LIM on the supply lines (Vss & Vcc).
Music playing at high SPL?
A contiguous groundplane under a SMD IC can couple sufficiently with the leadframe to lower leadframe impedance.
74LV574 comes in a range of packages, including VQFN-20 and TVSOP-20 with much smaller distances for the lead frames than SOIC.
Let us say that it is certain that we will see less LIM and clock/data feedthrough which cannot be a "bad thing".
Seeing that short FIR DAC's have high sensitivity to time inaccuracy, this would seem an obvious measures.
On paper at least 74ACT16374 has "better" (faster) timing than 74LV574, so it should actually be an improved replacement. However AC logic is know for massive ground bounce, so AHCT should probably be used.
Here timing is similar, a little worse for 74AHCT, 74LV lists 5nS minimum clock pulse, while 74AHCT lists 6.5nS. Switching timing is similarly worse, so we are looking at a 25% drop switching speed for 74AHCT16374, which is likely inconsequential in context.
Retain a dedicated section for the SR's.
It might, if we make it double balanced again.
Here a quick sim of my recommendation
4 X 1206 470n C0G
1 X 2220 100uF Pos-Cap (can use more)
4 X (series parallel) 8mm X 11mm 3F/2.7V Elna Dynacap DU
With Vcc & Vss planes we are looking < 60mOhm 10Hz - > 100MHz without obvious extreme resonances and an impedance minimum at ~10MHz.
Using more Pos-Cap reduce impedance below 10MHz:
Charging 3F to 5V will take some time. This needs to be carefully considered.
My approach is to use BOTH planes, Large value capacitors and small value capacitors. We now have a purely passive power supply comparably free from microphonics, electronic noise and with low impedance
If anyone makes new PCB's, it may be worth considering some improvements, be it smaller packages for the SR IC's, 16 Bit SR IC's, more layers etc.
Thor
Seems likely at some point I might make a new PCB. However, before trying to make a complete dac on one board, the thought here is to divide things up a bit first. Say, start by making an experimental shift register board, maybe with the Vref supply on it. Just study what actually works with the shift registers in terms of human perception of good sound (so far nonlinear caps haven't been a winner here, but layers are good). Once how to optimize that part is known, then start working towards consolidation.
To be exact, I meant bit clock harmonics, but if you find it clearer, you could also describe them as frequency components at integer multiples of the frequency of the second subharmonic of the shift register clock. I find that an unnecessarily complicated description of bit clock harmonics, but maybe you have a different preference.
The point is that the shift register clock is derived from the bit clock by a frequency doubler that makes a pulse for every bit clock transition. With any nonzero duty cycle error, or some asymmetry in the frequency doubler, the shift register clock will therefore have a second subharmonic at the bit clock frequency.
The bit clock frequency and its harmonics are also the only frequencies that cause only a small gain error when they end up on the reference or the clock. The reason is the repetitive spectrum of the digital input signal: they mix an exact copy of the audio band on top of the audio band.
You worry too much, only the non-harmonic LIM matters. That's not just theory; in my previous job, I have worked on embedded sigma-delta converters with only on-chip reference decoupling several times. One can only use a very limited amount of on-chip decoupling capacitance because of chip area constraints, so you get a relatively large ripple (LIM) on the reference. As long as you manage to properly cancel out data-dependence leaving only clock harmonics, it can work fine, make a design or layout mistake that causes data-dependence (or anything else that is not an exact multiple of the sample rate) and you are in trouble.
Maybe. One could try charging a big X5R capacitor to 5 V via a large resistor, subject it to loud music and measure how much AC voltage there is across it to see if the effect of loud music is large enough to worry about (or just use non-microphonic capacitors).
There is something weird about microphony: unless I totally misunderstood something, there is a forum member who uses class 2 ceramic capacitors without any issues in sensitive analogue electronics that are launched into space by rocket, yet bohrok2610's measurements seem to show that vibrations in an ordinary room give clearly measurable artefacts below 10 Hz when an X5R capacitor is used for reference filtering. Because of the capacitor's temperature dependence, temperature fluctuations could also cause voltage fluctuations, by the way.
Sure, but not by orders of magnitude as far as I know.
I use SSOP-20 with 0.65 mm pitch as a compromise between suitability for hand soldering and parasitics. It's cheating, really, as I did use SO for the logic gate DAC.
I don't think it is an objection, but it is something to keep in mind: supercapacitors have considerable dielectric absorption and their behaviour can change depending on how long ago they have last been charged. It's a bit like electrolytic capacitors, but with much longer time constants. I measured a 300 F, 2.5 V supercapacitor a couple of years ago:
The black (first charge) and blue (second charge) curves show the current through a 300 F supercapacitor that gets charged to 2.46 V, vertical scale in A, horizontal in hours. It was very slowly discharged over a resistor between the first and second charges. The initial current (which flows for about a quarter of an hour) is set by the current limit of the power supply, the rest by dielectric absorption and leakage.
The red and orange curves are attempts at modelling the dielectric absorption/leakage with RC networks. Red: two RC series networks in parallel, namely 68.33 ohm in series with 46.36 F and 431.6 ohm in series with 41.71 F. Orange: 68.33 ohm in series with 26.89 F and 431.6 ohm in series with 35.45 F. For reliability and lifetime, it is very important to keep their temperatures low.
Definitely.
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You somehow have to make sure the connectors between the boards don't mess up anything.
Marcel,
"There is something weird about microphony: unless I totally misunderstood something, there is a forum member who uses class 2 ceramic capacitors without any issues in sensitive analogue electronics that are launched into space by rocket"
I don't think these two things would exclude each other; while at launch there is tremendous vibration, (testing is up to 40G) - usually the experiments are only turned on while in orbit. There it could be 'cosmic silence' commanding already.. apart from position control.
"There is something weird about microphony: unless I totally misunderstood something, there is a forum member who uses class 2 ceramic capacitors without any issues in sensitive analogue electronics that are launched into space by rocket"
I don't think these two things would exclude each other; while at launch there is tremendous vibration, (testing is up to 40G) - usually the experiments are only turned on while in orbit. There it could be 'cosmic silence' commanding already.. apart from position control.
@bohrok2610 instead uses a system clock, which is probably a better choice for Jitter considerations.
There are further issues. There is a reason why serious clock distribution usually uses LVDS over LVCMOS. What happens on IC's Dies is a similar issue, but it still causes issues, just there is no fix.
I'm oldfashioned analogue/rf guy. Seeing this kind of junk on supplies worries me. Especially in A2D situations.
Which is why often for audio parts a separate pin encourages extra decoupling. The TI DAC's I favour have external decoupling for the current sources per channel (which are switched between L/N out) and a separate one for overall decoupling. Do it right and have quiet pin's and you get low HD.
Some "mistakes" are forced by poor IC pin layout.
No need to charge it. It's piezoelectric. Just connected to an "Instrument" input on a Pro-Sumer sound card (1MOhm, 100mV or so) and tap it with plastic pen.
Are they in guidance system that controls the rocket during take-off? Maybe the frequencies of the mechanical vibrations are sufficiently far from frequencies of interest to be filtered later?
Depending how exactly the supply lines are done, X5R (or Y5U for something that has the precise colour for what it is) can impact complete circuits at many frequencies.
Indeed.
Not orders of magnitude, but I work on the "6dB" rule. If small effort improves X that we worry about by 6dB, it's worth doing. I also learned the hard way that running active digital lines under ANY IC is a bad idea.
So I kind have it as a solid rule that directly under each IC should be a contiguous ground plane, followed by PSU planes (or rings in case of CPU's with a thermal pad and core + IO voltages).
The real ground plane is of course on the layer below the PSU and then we route on all available layers not the main ground plane or the main digital power plane which shall be the plane, the whole plane and nothing but.
As said, IDEALLY fast clock and data lines get a layer between real ground and Vcc planes.
So do other electrolytic capacitors and low grade ceramics. I leave gear with super capacitors permanently powered, unless away for more than a day.
SMA, FL? I prefer SMA as I can see them well.
Note that I suggest only rather linear capacitors. Anything Y5U or X5R is completely banned in anything I make. The more a ceramic capacitor tends towards the colour of excrement the more it is to be avoided.
The lighter excrement coloured ones really don't belong into audio gear, the darker excrement coloured ones are to be used only under extreme precautions and care, in applications where even a fraction of cent must be saved (e.g. Aerospace, Mil-tech etc.).
Thor
External reference decoupling has several disadvantages when the sigma-delta DAC or ADC is on a common chip with other circuitry (digital signal processing and a sensitive receiver, for example). You get a loop from the converter to the external capacitor and back that is sensitive to interference at all frequencies that are not exact multiples of the sigma-delta sample rate, that same loop also radiates at the sigma-delta sample rate and its harmonics, and the external capacitor gives customers an extra opportunity to mess up the circuit performance by poor layout. Sometimes external reference decoupling is inevitable, but when possible, I much prefer on-chip decoupling.
Well, doing that is usually a bad idea, if common.
Which is why I tend to use a small C0G next to the pin's (which ideally are next to the pin we close the loop to) and a "big old" (1210) film cap also close by.
Funny how most IC designers presume their customers are complete idiots. I'm not saying they are wrong.
But as Customer I find that having everything bonded out on pins that are are generally optional helps those customers who are not.
I remember one particular IC which used a charge pump to make a negative voltage. The datasheet was adamant to connect all +V pins to Vcc together.
Charge pump was isolated on one side of the IC (with power pad but separate GND pin at the CP) while other PSU pins for decoupling were on the other side of the IC.
Of course there was CP switching breakthrough everywhere with the "recommend layout".
It was a serious effort to get past the "tech support" who kept pointing me to the datasheet and kept reiterating what was written there to the actual IC designer who luckily still worked there.
I explained how I understood the workings of the IC, that is CP completely isolated to generate -V and should be connected to "dirty" Vss/Vcc and NOT the power pad under the IC and with a ferrite or inductor plus suitable decoupling Capacitors to keep CP noise contained. I added to use larger value CP and decoupling caps on the "Audio power pin's".
His dry reply was "that's how it was designed" and my enquiry why it was not in the datasheet resulted in a bit of unprintable stuff about field support and application people.
Applied as intended Miss Piggy kind almost became Claudi Schiffer, once adding an extra feedback loop and J-Fet Op-Amp, switched resistor ladder attenuator on a chip plus a single chip Battery Charger / Stepup, it turned into a killer solution for battery powered products, with > 3V SE output.
I digress, but really, I wish more IC designers would bond out internal nodes that can help those who know (what they are doing) get improved performance AND make sure it's at least in a secondary Datasheet Addendum.
Good example of what I like, Cirrus CS43131 - originally a Wolfson chip.
In "dumb mode" any engineer with chinese characteristics can make system that matches EVM performance.
But dig deep into the hidden stuff, and a lot more is possible.
As off-chip addition (on chip is still needed) usually helps performance, I prefer decoupling bonded out on pins.
Thor