I haven't done much listening yet.
The DAC board has been laid out for the default Eurocircuits four-layer stack-up with its double prepreg layer with a total thickness of 360 um. There are a few traces that need adjusting when the prepreg is much thinner or thicker than 360 um. The filter board is just a normal two-layer board.
What type and thickness of prepreg would you prefer for the DAC board?
The DAC board has been laid out for the default Eurocircuits four-layer stack-up with its double prepreg layer with a total thickness of 360 um. There are a few traces that need adjusting when the prepreg is much thinner or thicker than 360 um. The filter board is just a normal two-layer board.
What type and thickness of prepreg would you prefer for the DAC board?
Thanks Marcel. I did load the gerber zip file into JLC to get an idea of cost and it was reasonable but I haven't been able to determine their default stack. I'll enquire and also have a look at Eurocircuits and PCBway (as per the ValveDAC group buy) costs. I was looking at JLC because they offer a low-cost assembly service, though I've not looked into whether the KiCAD output includes the pick and place files as default. I'm thinking that a small batch of populated DAC PCBs might find some interest from others. I'm also prepared to hand solder if necessary.
Did you form any sort of impression from your limited listening?
Did you form any sort of impression from your limited listening?
Could I lend it to you? I've never been any good at listening impressions, and then you can judge for yourself if you find it worthwhile. You can then also check whether it works properly at the normal DSD rates (because of equipment limitations, I have only tested it at 27 Mbit/s) and whether it is really compatible with the usual USB interface and reclocking boards.
I expect that to be a great proposition since Nautiboy has a range of dac's, some very niche like your tube dac, which makes for easier comparison and it's relative position to your and other previous dacs.
Nice!
Nautiboy, up to the task? Would love to see the outcome of such a listening test.
Besides the tube dac, which other dacs would you, if you accept, compare it with?
Greetings,
Marco
Nice!
Nautiboy, up to the task? Would love to see the outcome of such a listening test.
Besides the tube dac, which other dacs would you, if you accept, compare it with?
Greetings,
Marco
I'm sure you are as skilled as I am at listening Marcel, but I'm happy to take up your kind offer and have a listen. I have some good power supplies, IIRC it requires +/-15V and 5V, and I have a JLSounds board I could use on the input so would be able to go to at least DSD256 with both 44.1KHz and 48KHz data families. The JLSounds has isolation and reclocking. Raw DSD would be via HQPlayer. To keep things simple I would listen via my valve headphone amp, this uses 300Bs and is very revealing and has a subjectively silent noise floor.
I normally run one of Pavel's DSC2 (Ver 2.5.2) based DSD decoders into my headphone amp - that sets a very high bar for a comparison. I could also hook up my ValveDAC, which nudges the bar a liitle bit higher. Those are the only two DACs I have working at the moment. I do have an AD1862 based R2R DAC project ongoing but I doubt I'll have time to get it running in the next few weks as I'm focussing on other projects first.
Ray
@MarcelvdG: Just another brief post to say that I don't really have that much more feedback right now - but as I said I would return Saturday or Sunday I prefer doing so. Maybe more in a couple of days - & interesting prospect of Ray listening to (some of) the various DSD designs made here on diyaudio in the last couple of years 
Cheers - Jesper
Cheers - Jesper
I found one more thing I would like to change: replace R14 with the series connection of an LL4148 and an 8.2 ohm resistor. As is, U1B can pull the supply voltage of U28 and U29 (clocksup_F) negative during power down, when its -15 V supply ramps down slower than its +15 V. I have changed this on my board and checked that everything still works, the schematic and layout are to be updated.
At start-up, the -15 V supply has to reach -0.3 V no later than 180 milliseconds after the +15 V exceeds +5 V. This is related to the common-mode input voltage range of U1A. You could get a too high voltage at U1A's output when you run it without negative supply, as long as that happens no longer than 180 ms, the voltage at C8 will not overshoot 5 V and no harm will be done. This requirement will easily be met by any normal dual power supply.
For the same reason, at power down, the -15 V should not become less negative than -0.3 V until the +15 V has dropped below 5 V. This will also easily be met, if only because the current drawn from the +15 V is much greater than the current from the -15 V.
Measured supply currents at 27 Mbit/s:
+15 V: 197 mA
-15 V: 51 mA
+5 V: 43.8 mA, 51.8 mA with a 101010... data pattern on both channels
Measured low-frequency roll-off with a 4965 ohm load from an output pin to ground, equivalent to 9930 ohm differential:
-0.1 dB at 40 Hz
-0.2 dB at 15 Hz
-0.4 dB at 10 Hz
-1.74 dB at 5 Hz
-6.99 dB at 2.5 Hz
-20.54 dB at 1 Hz
At start-up, the -15 V supply has to reach -0.3 V no later than 180 milliseconds after the +15 V exceeds +5 V. This is related to the common-mode input voltage range of U1A. You could get a too high voltage at U1A's output when you run it without negative supply, as long as that happens no longer than 180 ms, the voltage at C8 will not overshoot 5 V and no harm will be done. This requirement will easily be met by any normal dual power supply.
For the same reason, at power down, the -15 V should not become less negative than -0.3 V until the +15 V has dropped below 5 V. This will also easily be met, if only because the current drawn from the +15 V is much greater than the current from the -15 V.
Measured supply currents at 27 Mbit/s:
+15 V: 197 mA
-15 V: 51 mA
+5 V: 43.8 mA, 51.8 mA with a 101010... data pattern on both channels
Measured low-frequency roll-off with a 4965 ohm load from an output pin to ground, equivalent to 9930 ohm differential:
-0.1 dB at 40 Hz
-0.2 dB at 15 Hz
-0.4 dB at 10 Hz
-1.74 dB at 5 Hz
-6.99 dB at 2.5 Hz
-20.54 dB at 1 Hz
Hi Marcel,
On and off "simmering" about your RTZ DAC ... A couple of thoughts have come up here ... :
-Wouldn't it be somehow possible to - hopefully simply - "adjust" the RTZ design in a way so that the output level is just marginally reduced? Something in the way KSTR mentioned - implementing RTZ time-wise to the extent that it does what it is supposed to do but only works in a shorter time span & thus allows for a higher output level ..
- Also, you are using a frequency doubler in your design. Will it not produce harmonics - sort of what you identified in Andrea Mori's doublers - which may affect both the sound & the measured response?
Just a couple of thoughts - cheers,
Jesper
On and off "simmering" about your RTZ DAC ... A couple of thoughts have come up here ... :
-Wouldn't it be somehow possible to - hopefully simply - "adjust" the RTZ design in a way so that the output level is just marginally reduced? Something in the way KSTR mentioned - implementing RTZ time-wise to the extent that it does what it is supposed to do but only works in a shorter time span & thus allows for a higher output level ..
- Also, you are using a frequency doubler in your design. Will it not produce harmonics - sort of what you identified in Andrea Mori's doublers - which may affect both the sound & the measured response?
Just a couple of thoughts - cheers,
Jesper
For reasons of sensitivity to jitter (jitter related to far-off phase noise, to be precise), I like to turn on the odd taps with the same clock edge that forces the even taps to zero and the other way around. Increasing the duty cycle of the even taps then reduces the duty cycle of the odd taps, so it doesn't help. I will have to draw a timing diagram to show you what I mean.
The problem with frequency doublers is related to subharmonics of the sigma-delta modulator's clock frequency. Some of Andreas' oscillators worked at the second subharmonic and used a doubler to make the full clock frequency, with some second subharmonic leaking through. The second subharmonic is exactly where a single-bit sigma-delta modulator is most sensitive to interference. The doubler I use only produces harmonics of the sigma-delta clock frequency, no subharmonics.
The problem with frequency doublers is related to subharmonics of the sigma-delta modulator's clock frequency. Some of Andreas' oscillators worked at the second subharmonic and used a doubler to make the full clock frequency, with some second subharmonic leaking through. The second subharmonic is exactly where a single-bit sigma-delta modulator is most sensitive to interference. The doubler I use only produces harmonics of the sigma-delta clock frequency, no subharmonics.
This is an oversimplified schematic of the DAC, drawn single-ended and unloaded for simplicity. When you look at the transitions at the output, you will see some switching spike and a transition to the next value. In half the cases, the next value is (except for resistance tolerances, including shift register output resistance differences) the same as the previous value: from (D0 + D1)/4 to (D0 + D1)/4 or from (D1 + D2)/4 to (D1 + D2)/4. In the other half of the cases, only one of the averaged data bits is replaced with a new one: (D0 + D1)/4 to (D1 + D2)/4.
When the clock transition is not exactly at the right moment, shifting the transition from (D0 + D1)/4 to (D0 + D1)/4, the switching spike will shift, but otherwise almost nothing changes. In particular, the average value over the two clock cycles stays the same except for some small effect of resistance tolerances. If the odd and even taps were clocked by different clocks, shifting an edge of one of them would immediately affect the average voltage, that is, the low-frequency content. Hence my preference for using the same clock.
When the next clock transition is not exactly at the right moment, shifting the transition from (D0 + D1)/4 to (D1 + D2)/4, the low-frequency content will be affected whenever D0 and D2 have different values. If I had used a long shift register, I could claim that as only one bit changes, the average is always affected far less than with separate clocks for the odd and even taps. For example, with 16 taps, it would be a transition from (D0 + D1 + D2 + D3 + D4 + D5 + D6 + D7)/16 to (D1 + D2 + D3 + D4 + D5 + D6 + D7 + D8)/16.
Still, even this short shift register is quite useful because it suppresses quantization noise around half the sigma-delta clock rate (equivalent to four shift register clock cycles, as the shift register runs at twice the sigma-delta clock rate). Single-bit sigma-delta modulators typically produce lots of noise and tones near half the sigma-delta clock rate, which implies that the chance of D0 and D2 having the same value is substantially higher than in a pure random bitstream.
Hi Marcel,
& once more thanks for your very helpful & educating feedbacks ... It seems I will just have to ponder what you say in #95 for a bit of time to grasp (more) of it ...
In relation to the clock doubler you use - does it then mean that in this context there are no "real" shortcomings to it e.g. compared with Andrea's doublers?
Cheers,
Jesper
& once more thanks for your very helpful & educating feedbacks ... It seems I will just have to ponder what you say in #95 for a bit of time to grasp (more) of it ...
In relation to the clock doubler you use - does it then mean that in this context there are no "real" shortcomings to it e.g. compared with Andrea's doublers?
Cheers,
Jesper
Thanks, Marcel, for the clarification.
WRT #95 I reckon that this principle of averaging may be applied to any DSD DAC outside of the pure 1 bit version? I.e. one could use 4, 8, 16, 32 etc. taps on the output to average out quantization noise - is that correct? If so, and besides component count increase - isn't there any shortcomings of doing so? I am thinking that the averaging, well, "averages", so that maybe the speed of such a DAC diminishes with increased No. of taps? Or maybe distortion distribution changes ...?
Recently I have been trying out a 1 bit DAC (NoDAC approach), and although I haven't yet succeeded in getting it beyond - 86 dB THD (components were damaged so I am awaiting new/replacement components) the distortion spectrum indeed looks benign. 2H at approx. - 88 dB and 3H 20 to 30 dBs lower. No visible higher order harmonics - but noise floor at ~ -115 dB as the output level is low (-36 dB ref 3.4V). Sounds like a different distortion spectrum compared with the RTZ DAC's ... ?
Cheers,
Jesper
WRT #95 I reckon that this principle of averaging may be applied to any DSD DAC outside of the pure 1 bit version? I.e. one could use 4, 8, 16, 32 etc. taps on the output to average out quantization noise - is that correct? If so, and besides component count increase - isn't there any shortcomings of doing so? I am thinking that the averaging, well, "averages", so that maybe the speed of such a DAC diminishes with increased No. of taps? Or maybe distortion distribution changes ...?
Recently I have been trying out a 1 bit DAC (NoDAC approach), and although I haven't yet succeeded in getting it beyond - 86 dB THD (components were damaged so I am awaiting new/replacement components) the distortion spectrum indeed looks benign. 2H at approx. - 88 dB and 3H 20 to 30 dBs lower. No visible higher order harmonics - but noise floor at ~ -115 dB as the output level is low (-36 dB ref 3.4V). Sounds like a different distortion spectrum compared with the RTZ DAC's ... ?
Cheers,
Jesper
Interesting that your third harmonic level is much lower than my -95 to -90 dB. The even harmonics should largely cancel when you make a balanced version.
Regarding the taps, the FIRDAC also filters the desired signal. With an unweighted averaging over a time n T, where n is the number of taps and T the delay from tap to tap (usually a sample period or half a sample period), you get a sin(pi f n T)/(pi f n T) response. There are deep notches at f = 1/(n T) and its nonzero multiples, and the response is already down to 2/pi or about -3.92 dB at f = 1/(2 n T). So the treble loss you are willing to accept, the sample rate and whether the delay from tap to tap is 1 or 1/2 sample time determine how long you can make a uniformly weighted FIRDAC.
Regarding the taps, the FIRDAC also filters the desired signal. With an unweighted averaging over a time n T, where n is the number of taps and T the delay from tap to tap (usually a sample period or half a sample period), you get a sin(pi f n T)/(pi f n T) response. There are deep notches at f = 1/(n T) and its nonzero multiples, and the response is already down to 2/pi or about -3.92 dB at f = 1/(2 n T). So the treble loss you are willing to accept, the sample rate and whether the delay from tap to tap is 1 or 1/2 sample time determine how long you can make a uniformly weighted FIRDAC.
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