I was positively surprised by -90dBc/Hz at 10 Hz :-D It doesn't necessarily mean I'm content with it but still... 😉
Otherwise no surprises.
Sören makes SQ claims, you make technical performance claims - your can be verified, Sörens is harder.... Maybe there exists at least one person that indeed think the DAM is better then the named products... and that it is the "absolute best". Also, I think it was a forward looking statement as I think the product was under development when he wrote that. But I agree, I don't think he did achieve his goals. Again, defining something a reference doesn't mean it has to be the "best" but many tend to think so.
//
Otherwise no surprises.
Sören makes SQ claims, you make technical performance claims - your can be verified, Sörens is harder.... Maybe there exists at least one person that indeed think the DAM is better then the named products... and that it is the "absolute best". Also, I think it was a forward looking statement as I think the product was under development when he wrote that. But I agree, I don't think he did achieve his goals. Again, defining something a reference doesn't mean it has to be the "best" but many tend to think so.
//
There is missing a crucial information for the inexperienced
You need to rescale the plots by 20 log_10(f/F) if you compare clocks of different frequency f and F to be fair.
"The phase noise plots talk themselves, no needs of explanation."
Please, for us less knowing....
//
There is nothing to rescale.
The curves in the first two plots are all at 2.822 MHz and 3.072 MHz.
Just in case the state of the art oscillators are penalized since they run at double frequency.
The third plot compares the LRCK in against the LRCK out, that's just what concernes the jitter reduction, regardless of the frequency.
The phase noise is an absolute value.
Yess but your DRIXO runs on double frequency so it is penalised - correct should be correct!
//
//
The DRIXO was reported just for reference, so if you want you can subtract the theoretically 6dB from its curve.
But I have several doubt its phase noise could improve dividing by 2, it's in the "class" of the best oscillators on the market (objective measurement), very difficult to do better.
In the third plot you compare 192kHz clocks against one of 16 times higher frequency. The later needs to be shifted 24 dB down (at least in the part above the noise floor of the clock).
As that would be the theoretical result you obtain if you divide the faster clock down to 192kHz and measure it then. Otherwise you compare apples and oranges.
No, you don't understand.
The comparison is between the input LRCK and the output LRCK just to understand the claimed jitter reduction.
It has nothing to do with the LRCK frequency, that's a design choice.
It's not me who have chosen to run the DAC at these high frequencies.
Our DACs will run with 5/6 MHz master clock (far away from 45/49 MHz of the DAM1021) and the max LRCK frequency will be 192 kHz (maybe 384 kHz, to be tested).
You confound (again) jitter and phase noise.
My altruism for today is used. I won't comment further of your "facts".
My altruism for today is used. I won't comment further of your "facts".
Last edited:
This is however insulting as I see it - to go to someones party and say that the soup is off - quite rude. Despite if you where invited or not - so "You asked me to come so I feel I can say whatever I want about the soup" doesn't cut it. Especially of you are a so-chef.
//
//
Last edited:
Are you referring to the SBAF measurements of the dac2541? I’m still thinking what the reason is for its low jitter, in comparison to your measurements.
- Si570 instead of Si514 (not miles ahead so can only account for so much)
- lower noise power regulators (again only so much unless PSU was terrible before)
- reclocking after FPGA (getting there...)
- different make of FPGA with larger FIFO and so possibly different software?
So this is probably wishful thinking but if anyone could measure the dam1121 in comparison we could start drawing conclusions.
The 570 is quite a lot better than the 514, in the region of 20dB lower phase noise at 100Hz.
Oscillator Phase Noise Lookup - Silicon Labs
Thanks for reminding me that’s not something to downplay — even when not in the same league as the dedicated clocks Andrea is referring to.
Last edited:
I would be interested in the phase noise of the DAM1021 with the oscillator running on its own (no input) vs. clocked over S/PDIF. This would show if and how the corrections ("wander") actually affect jitter.
You are confused, phase noise and jitter are the same indicator but expressed from a different point of analysis, phase noise in frequency domain and jitter in time domain.
Please look carefully to the plots, they contains both phase noise spectrum and jitter values.
Indeed they are mathematically related, you can calculate the jitter starting from the phase noise using a suitable integration bandwidth.
Due to the arbitrary value you can assign to the integration bandwidth that can alter a lot the jitter value, the phase noise is preferable because it's an absolute value.
And also the phase noise shows the spectrum of the noise while the jitter is a standalone number that does not explain nothing about the distribution of the noise.
It looks like you have to study a little, so maybe you will understand because the Allan Deviation measurement is useless in digital to analog conversion.
Last edited:
Sorry, but I have already spent EUR 350 for the DAM1021, so I stop here.
I prefer to spend money building my own DAC.