A 1941 should do that if the signal comes via USB. So that's a way to see if this has any impact.
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I ended my professional career 2 years ago leaving a network system department on one of the bigger telecom companies - which? /// 🙂 I have at least one patent in transmission and delt with NW synchronisation question through the years. I offer my help, for free, as a project leader to run a short stint to investigate, prototype and evaluate an improvement of the clock aspects in the DAM. I would program if I could but alas I cant help there I regret.
Will work for food and a place to lay my sleeping bag :-D
I'd love to see Denmark again.
BR // TNT
Will work for food and a place to lay my sleeping bag :-D
I'd love to see Denmark again.
BR // TNT
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Very good @TNT, I was always curious about the clock adjustments myself after noticing them when I had a very jittery clock on my ADC once upon a time. With a very solid clock from a good quality usb-i2s adapter the dam1021 clock should be readjusting as little as possible right? The fact that a 1941 can lock to the usb source is also telling, why we cant have such a firmware option for the i2s input when an upstream clock is present....
I can not take praise for the tracings. They where made by an other diyaudio member - you know who you are....
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If I interpreted the programming part of the data sheet of the clock correctly, your data shows that the old statement that the clock is updated in 1Hz steps is still valid.
Very roughly, if the hex number at position "Data write: 05" goes up/down by one the frequency goes up/down by one Hz.
Could you make from that a plot from your data where one sees the oscillation in Hz?
Moreover for the project for a better clock algorithm
the following could be useful: The clock can be incremented in finer steps (about 8 bits more resolution). The time needed that clock needs to settle after a new setting is about 100mu seconds.
Hex 55 is the device adress. By looking at one logical command (e.g. a freq adjustment) towards the Si (i.e. all the writes above), one cant draw any conclusions. But I understand what you mean. I'll see what I can do. Still, I personally would not be in favour of a "many continuously small adjustments". Really, a decent osc today are very stable long turn (sec, min, hour) around it's center frequency, only jitter exists - this jitter is so small that a very small buffer i.e. 1ms should be able to digest it easily - ending up with almost no need (0, 1 or 2?) to do clock adjustment along playing a track of music. Find the centre frequency and fill the buffer to half, stop adjusting the clock and play music 🙂 So if there are a few "broken" sources out there that will not play - you don't want them to feed your DAC anyways and reports from these constellations wrt. SQ do better not surface at all.
I would like to hear the DAM playing music with its clock untouched for a couple of minutes - it would be interesting.
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I would like to hear the DAM playing music with its clock untouched for a couple of minutes - it would be interesting.
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No, it is always on. How else can the fifo function?
One day, if we are lucky, there may be a diy dac of this kind which accepts an external clock and has no fifo. Inshallah 🙂
One day, if we are lucky, there may be a diy dac of this kind which accepts an external clock and has no fifo. Inshallah 🙂
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To my current best understanding and as analog_sa says, yes. Always and in all situations, it's working like this.
This particular trace was made on a I2S fed DAC.
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This particular trace was made on a I2S fed DAC.
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Troubleshooting help. I have a recent 1021 board, purchased earlier this year. It plays wonderfully with I2S...however I can't get the twisted pear toslink board to lock...manual or auto sense.
The board is set up TTL(not real clear if this is correct...DimDim's blog led me to this conclusion and the 1021 manual show a ultra simple connection), and I'm feeding +5V from pin 6 J2. Output of the onboard reg is 3.3V. Output is on pin 9 J3.
Source locks with another DAC.
Anything else worth looking at before I rip it out completely?
Thanks!
The board is set up TTL(not real clear if this is correct...DimDim's blog led me to this conclusion and the 1021 manual show a ultra simple connection), and I'm feeding +5V from pin 6 J2. Output of the onboard reg is 3.3V. Output is on pin 9 J3.
Source locks with another DAC.
Anything else worth looking at before I rip it out completely?
Thanks!
I have pondered about this but have done no measurements to either prove or disprove it. It certainly makes sense: same clock is driving both Xmos and fifo and asio driver is responsible for keeping Xmos buffer happy. So, no need to vary clock frequency.
But is this only speculation, or is there some solid evidence? Like measurements, or Soren confirming it?
I must be blind. Thank you!
In the 1941 thread i mentioned the quality of the onboard Xmos interface surprised me pleasantly when compared to what i had as a reference: a JLSounds Xmos connected via i2s. I suspected the elimination of close clock frequencies and their potential interference was the reason, but the fixed clock offers a much better explanation.
Unknowingly, i had been listening to the experiment TNT was proposing and while i gave some preference to the fixed clock, the difference was not all that big. So, to my ears at least, the issue of the constant clock adjustments is not so important.
Perhaps the more audibly important advantage of the 1941 is the output reclocking in FPGA.
In the 1941 thread i mentioned the quality of the onboard Xmos interface surprised me pleasantly when compared to what i had as a reference: a JLSounds Xmos connected via i2s. I suspected the elimination of close clock frequencies and their potential interference was the reason, but the fixed clock offers a much better explanation.
Unknowingly, i had been listening to the experiment TNT was proposing and while i gave some preference to the fixed clock, the difference was not all that big. So, to my ears at least, the issue of the constant clock adjustments is not so important.
Perhaps the more audibly important advantage of the 1941 is the output reclocking in FPGA.
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Are still making these boards? I ordered a 1021-12 thru Mod House Audio your US distributor but I haven't heard from them in months. And I'd like to get on with the project. thanks
Hi Soekris
I found my mistaken when connecting the amanero to dam1021, so I am very sorry to you when i write a comment here in this topic, but i do not know that.
Thanks for your help.
Mod note. Please see post #8528 for new image.