Hi Soren
Just seen this. Very nice design Ill certainly be interested in one when they become
available (0.02%).
Just one question. I see you run the LVC595 from a negative power rail. Last time I
tried this it didnt work (though it wasnt with LVC logic). Are you doing anything
special or does it just work?
Just seen this. Very nice design Ill certainly be interested in one when they become
available (0.02%).
Just one question. I see you run the LVC595 from a negative power rail. Last time I
tried this it didnt work (though it wasnt with LVC logic). Are you doing anything
special or does it just work?
Last edited:
The LVC parts don't really care aboout the absolute voltages, only the difference between VCC and GND....
One set of LVC latches have +4V on VCC and 0 on GND, the other set have have 0 on VCC and -4V on GND
Søren, can you please expand on this design decision?You're correct on that, and I have actually done some thinking about it, ended up having the resistors for the 14 MSB bits be the best precision ones, with the 13 LSB bits be one grade less precise, like the 0.02% version have 0.05% resistors on the 13 LSB bits, to keep cost down but still having great performance when using the digital volume control. Could in principle use less and less precise parts going down on the bits, but it's again a question about not having too many different almost alike parts. Give an EMS provider an opportunity to mess up and they will take it....
The prototypes have 0.05% ones on the 14 MSB bits, with 0.1% ones on the 13 LSB bits.
And I really should do some Monte Carlo analysis, but as I'm not a serious math guy I'm just using gut feeling as guide for now
What would be the difference if in the 0.02% version, 0.02% R's would have been used for the LSB's instead of 0.05%?
What would the (price) implications be for the 0.05% version if the entire ladder would be 0.05%?
Last edited:
Hi Soekris,
What a fantastic project! Incredibly well thought out, beautifully laid out, and unique to boot!
Please put me down for two boards with 0.01% resistors.
I can run a full suite of measurements on an APX525 when I get my boards, which should provide more accurate results compared to the sound card you're using now.
Keep up the good work!
Regards,
Owen
What a fantastic project! Incredibly well thought out, beautifully laid out, and unique to boot!
Please put me down for two boards with 0.01% resistors.
I can run a full suite of measurements on an APX525 when I get my boards, which should provide more accurate results compared to the sound card you're using now.
Keep up the good work!
Regards,
Owen
Last edited:
Hi Soekris,
very interesting project, I hope you'll get also good results.
Only a few questions.
Since in the early 90's I had a bit of problems to eliminate the glitch from a digital volume control, I'm curious if you have solved the issue in your DAC. As far as I understood the sign magnitude topology does not eliminate the glitch itself.
Can you explain the clock line of all the DAC, from the input to the output?
I see you are using the Si514. As I wrote in another thread I don't like much these type of master clock, since they don't perform very well in phase noise (-86 dBc/Hz at 100 Hz from the carrier at 156 MHz), but I understand if you have to manage different sample rate you cannot implement several fixed crystal oscillators.
If I understood correctly you detect the sample rate from the incoming signal, then you store the data in a FIFO, and after?
Where do you take the clock for the LVC595?
The last question, related to the previous: what happen to a classic CD signal, 16 bit 44.1 kHz, is it upsampled to 176 kHz? or what else?
Sorry for the questions, but since this is a very original project, I would know your design choices.
Thanks
Andrea
very interesting project, I hope you'll get also good results.
Only a few questions.
Since in the early 90's I had a bit of problems to eliminate the glitch from a digital volume control, I'm curious if you have solved the issue in your DAC. As far as I understood the sign magnitude topology does not eliminate the glitch itself.
Can you explain the clock line of all the DAC, from the input to the output?
I see you are using the Si514. As I wrote in another thread I don't like much these type of master clock, since they don't perform very well in phase noise (-86 dBc/Hz at 100 Hz from the carrier at 156 MHz), but I understand if you have to manage different sample rate you cannot implement several fixed crystal oscillators.
If I understood correctly you detect the sample rate from the incoming signal, then you store the data in a FIFO, and after?
Where do you take the clock for the LVC595?
The last question, related to the previous: what happen to a classic CD signal, 16 bit 44.1 kHz, is it upsampled to 176 kHz? or what else?
Sorry for the questions, but since this is a very original project, I would know your design choices.
Thanks
Andrea
A R-2R network i a weighted network, so MSB is 1/2 the value, MSB-1 is 1/4 the value, MSB-2 is 1/8 the value and so on.
So the precision of the LSB has not much influence on the total precision. I keep 14 MSB bit at full precision because of the digital volume control, the digital volume control is kinda "expensive", but in my opinion important as it really is perfect....
The cost of the resistors for the 0.05% version is maybe 20% of the total part cost, but I'm trying to keep cost down on especially the 0.05% version, so more people can enjoy the sound
I have a simple solution to that: The LVC data and clock signals are all capacitive coupled, you just need to have all the signal with 50% duty cycle....
Ok... I understand that the total influence is limited. The relative influence however is bigger.. I do not know the difference in price between 0.05% and 0.1% resistors, but I guess it is less than the difference in 0.05 and 0.02%.So the precision of the LSB has not much influence on the total precision. I keep 14 MSB bit at full precision because of the digital volume control, the digital volume control is kinda "expensive", but in my opinion important as it really is perfect....
The cost of the resistors for the 0.05% version is maybe 20% of the total part cost, but I'm trying to keep cost down on especially the 0.05% version, so more people can enjoy the sound
Could you please give me an estimate of the price difference when 0.05% resistors are used in stead of 0.1%? If it is less than $20 I could live with it..
BTW: to me the digital volume control is less important
The advantage of the sign magnitude DAC is that the MSB bits are not switching if there is no need to, so you don't have high levels switching noise going into low level signals more than absolute necessary, in contrary to a regular DAC where the MSB are always switching as the signal crosses zero.
There is the incoming audio, with the associated bit clock. That are feed into a FIFO, and can be pretty "dirty"...
The there is the clock to the DAC, almost directly from the Si514 clock generated, only divided down as needed.
The uC measure the input clock and adjust the DAC clock as needed, the Si514 can be adjusted in small steps up to 1000 ppm without glitches at output.
The FIFO takes up any difference, the size of the FIFO decide the latency and how much difference it can accept before the clock need adjusting...
My DAC is not different than other DAC's in handling upsampling, except that my DAC can be customized.... There has already been long discussion elsewhere about that, so I wont go into that here.
I have already worked on tradeoff between price performance and ended up with three version, don't want to make more....
If you want all 0.05% or better you need to buy the version with 0.02% and 0.05% resistors.
If you want to know cost of the resistors, Digikey have them all....
That helps but doesn't eliminate the glitches. At any time one or more bits are switching, MSBs or not, causing less or more switching noise.
You don't care about low level switching anyway?
What do you mean "almost directly"? Are the shift register clocked directly from the XO or just from the FPGA? Where do you make the division?
Ok, I was not clear here. Is there anyway upsampling or not?
If you feed the dac with a 16 bit/44.1 kHz signal, do you get the same at the network ladder?
Or just the DAC operates anyway at higher speed?
What is the master clock frequency in this case?
Sorry, I read all the thread but I don't understand what can be customized and what is fixed from the projectual choices.
> The advantage of the sign magnitude DAC is that the MSB bits are not switching if there is no need to, so you don't have high levels switching noise going into low level signals more than absolute necessary, in contrary to a regular DAC where the MSB are always switching as the signal crosses zero.
The disadvantage is that the positive and negative supplies have to be matched and thermally tracked to say 1ppm, or else a sine wave will have different amplitudes in its positive and negative halves.
Perhaps you can share with us how this is implemented ?
Patrick
The disadvantage is that the positive and negative supplies have to be matched and thermally tracked to say 1ppm, or else a sine wave will have different amplitudes in its positive and negative halves.
Perhaps you can share with us how this is implemented ?
Patrick
In my opinion, thanks to the relative low resistance of the R's and compatch SMD design, the switching noise is low enough so it don't affect the sound quality.
Si514 -> FPGA divider -> LVC595, with shortest and fastest path possible.
Any of it, you choose.... The DAC will come as standard with 8-16 times oversampling filters, but you can create and load new sets, including no filters. The master clock will run in lowest frequency needed.