Preventing Sansui AU-X1 output stage oscillation burn out

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Hi.
View attachment 1285668
680 + 1 nF.
By many signs, I see that the Japanese knew what they were doing.

View attachment 1285669
For example, this type of compensation indicates the application of Nyquist stability criteria. Almost no one has done this in serial amplifiers, at least I have not seen it. I sincerely take my hat off to these specialists.

All changes proposed by you should be made only and exclusively after calculating the characteristics in LT-Spice. For example, we are used to putting the Zobel circuit to the right of the coil, since the stability of the amplifier is provided by internal compensation. The use of the Zobel circuit was appropriate for quasi-complementary output stages with an unstable couple Shiklai in the lower arm.
With best regards!
It can't be 680 and 1nF as that sets the -3dB bandwidth at 234 kHz - that would show up on a frequency response test. They are quoting DC to 500 kHz.

The arrows you point to above are not part of loop compensation. The 47 Ohm resistor across the JFET sources sets gain - it's not a loop compensation component. The 22 pF cap is likely for local stability reasons, or to balance the gate load capacitance between the two halves.

Placing the Zobel AFTER the output coupling coil is not considered best practice for the reasons I gave earlier - and especially so if you are using an EF3 which easily oscillates at HF without precautions or sloppy layout. Looks like they corrected it on later models though.

I just noticed the VAS outputs are also loaded to 0V with 39k resistors. You see this on a few amps of this vintage and it's usually being done to try to flatten the loop gain. At around this time - and still prevalent in some circles today - there is the mistaken understanding that if an amplifier's loop gain or open loop gain bandwidth is low, it will not be fast. As explained in many texts on feedback (Jan Didden also did an article on this specific issue a few weeks ago), this doesn't make the amp faster. Opamps that slew at 100 V/us have -3dB open loop bandwidths of <10 Hz and full power bandwidths of 200 kHz.

The diode chain you show looks to me to ensure the pre-driver and driver don't saturate - only the VAS transistor can. Since the VAS device is usually faster than the drivers, it should recover more quickly if overdriven. This copuld be an issue in this amp because the VAS and front end are supplied off a higher voltage than the OPS.
 
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You can shape loop gains of >120 dB to ensure adequate gain and phase margins at the ULGF rater than loading the gain out. It may require more than one pole - zero pair (so 3 or 4 pole compensation) in the comp network, but it is doable. However, my personal opinion is why do it when below a certain level, distortion is not audible? You are just creating complexity.

Ed, you still have the integrator function via the caps returning to the inverting input - at some point, the VAS stage gain has to be curtailed if there is to be any chance of stability since the OPS ultimately sets the ULGF and the available phase margin. By comping the amp like this, the amount of current available to charge and discharge the comp capacitors is greatly increased. If they had used standard miller comp, the quoted slew rate 260V/us would have been difficult to achieve. It is still an integrator stage.

The VAS is loaded in the manner shown in the Sansui circuit almost certainly to flatten the loop gain response, and they used very small Miller caps to try to maximize the loop gain before flattening it out with the 39k load resistors. A lot of these vintage design approaches were based on misconceptions and are discussed i.a.o by Cordell, Self, Putzeys and recently in Jan Didden's audioXpress article.

Smersh, your comp method (I've seen that before) does not look the same as the Sansui circuit if I am reading it correctly. You don't have access to the internal sources (or emitters) of the opamp input devices. In the Sansui circuit, the resistor is connected directly across source to source and the 22pF cap goes from the n-inv input to the same device source. Surely that is not the same?
 
Bonsai - The 3pF capacitor around the VAS is technically an integrator, but only above 400KHz. It is the third pole that I see in the Sansui amplifier.

The dominant pole is at 30KHz from the 680pF capacitor after the input FETs. The 120KHz pole is on the VAS output. I also see two zeros, one from the 470ohm resistor and other from the 1pF lead capacitors. I can tell that Sansui had a hard time making this amplifier work. ;)

Everyone knows that the loop gain must be brought down to unity before the phase shift becomes excessive, but now it seems that we have forgotten all ways to do that other than by putting a Miller capacitor around the VAS.

My specific complaints about the Miller capacitor are that it degrades the PSRR at high frequencies, and having two parallel capacitors (integrators) in a complementary amplifier creates mistracking. I prefer a frequency compensation method that does not have these downsides.

There were a lot of misconceptions about feedback, but there were also a few good approaches.
Ed
 
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I used a 4.7pF cap in Miller fashion the same way Sansui has in this TMC compensated amp: https://www.ovationhifidelity.com/product/model-1721/

The main comp components were configured in TMC loop with a ULGF of 1.5 MHz - the 4.7pF caps were there to tweak the phase margin at the ULGF. The TMC still formed an integrator, but like the Sansui (which is a VFA), there was plenty of current from the VAS stage to charge and discharge the comp caps. Normally, the peak current into the comp cap in a standard Miller configuration would be limited to whatever the front-end stage could provide - in any event, lower than the alternatives discussed here. Note, operation of the linked to amp above is a little different, other than TMC vs how Sansui did it, because it is a CFA
 
I think we are just arguing about the definition of "integrator".

A true integrator will integrate DC. Practical integrators have a corner frequency below which they stop integrating. The corner frequency may be 100Hz or 40KHz depending on the design. Both are entirely workable design points.

Since my resources are limited as a hobbyist, I go with what I can design reliably. That has been one-pole (just not Miller) placed above 20KHz. The end result is... no-one could hear a difference. ;)
Ed
 
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madis64 - I usually don't respond to posts about subjectives, but...

No-one has ever commented about my amplifier because it has no sound about which to comment. All good amplifiers sound the same regardless of how they were designed.

People comment on the Maggies because they really do sound different than box speakers.

My two-cents for people who hear differences between amplifiers is that one or more of those amplifiers is not-so-great.
Ed
 
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2. The OPS is an EF3 if I'm reading the schematic correctly. These are prone to instability unless treated with care - again, Self and Cordell discuss this in-depth (see especially Cordell).

Yes. There are very high probability of instability.
Place something like 100-150 Ohm in red circles between first and second followers.
Place something like 100-300 pF in blue line between base and collector of the second follower.

Sansui.PNG
 
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madis64 - I usually don't respond to posts about subjectives, but...
Well, you cannot really assume that subjective posts do not receive subjective responses ;)
My two-cents for people who hear differences between amplifiers is that one or more of those amplifiers is not-so-great.
Take the same - subjectively (or even objectively - by measurement results) - "great" amplifier which goes straight (by objective measurements) e.g. up to 80 kHz and place a 20 kHz low pass filter in the signal path. I think (I have actually never done such a thing myself so I cannot say that I know) that you will hear the difference.
Amplifier is the same, only input signal is filtered.
Subjective me ;)
 
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The power supply rails are at 0V to AC because of the PSU caps. The advantage of this is you are not injecting HF signal currents into the ground network, but instead the rails where you get some PSRR rejection help and the HF signal currents are routed back to the star ground, assuming the board it laid out correctly.
 
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Just a side question - why are such caps placed between base and collector when collector is connected to the voltage rail and not between base and earth?
Connecting the capacitor between the base and collector minimizes the inductance as seen by the transistor. This connection also creates a path for high-frequency noise to couple from the supply rail to the signal, but that is less problematic than inductance.
Ed