Preamp with LS Jfets

[qwertyl]

There are very rare situations where pot at the preamp's output isn't a bad idea and this is not one of them.

Many had the same idea before (do something differently from the mainstream, at any cost) but in the end it boils down to this (post #500) :
LSK pre - BAF 2013

I see that you are primarily interested to get a confirmation for your idea so go ahead, it's easy to try both (pot at the input and pot at the output) and keep what you like better.

Not at all, just considering various options. Thanks for your advice - pot at the input it is then

 

[lineup]

This was presented at BAF four years ago, and I thought I had written
it up, but if I did I can't find it.

Here's the graphics of a nice line level gain stage which has no loop feedback.

Great circuit, Nelson!

That it uses all FETs from LS is an additional plus.

I wonder what is the approximate Vgain of your circuit in first post?
Can one change the gain a bit .. and if so, how?

 

[Nelson Pass]

The response graph shows the gain at 15.5 dB.

You can adjust the values of R3 and R6 over a fairly wide range.

As you increase R3 the gain goes down and vice versa.

As you increase R6 the gain goes up and vice versa.

 

[lineup]

Thanks Nelson.

Anybody knows where one can buy those transistors?
Is the only option at BIFET, JFET, INTERFET, Diodes, Transistors, DMOS, MOSFET homepage?

 

[Telstar]

There should be retailers that carries them in EU.

 

[lineup]

okay, that is fine
I keep on searching

 

[vdi_nenna]

Voltages

I have another bonehead question. I watched the BAF 2013 video several times over the years since released, but still baffled by the voltage requirements.

Reference schematic for LSK Preamp in first post.

The circuit can run off +/-45v, and the input and cascoded jfets need 30mA.
However, when describing the jfet output buffer to lower output impedance, There's talk about the jfets can only handle around 25v.
Why can the input and cascade jfets handle 45v and the buffer cannot?

I know R4 and R5 provide 30mA
Is there a voltage drop provided by the 1k R4 & R5 that lowers the rail voltage?

Does the jfet themselves and R3 come into play in lowering/adjusting the voltage to another level?
Kirchhoff's Law come into play? All the voltage drops must equal 45v?

 

[Zen Mod]

see 18V marked ?

these JFets (in post #1) are seeing 18V from D-S

include buffer stage , cascode it regularly to 12-15-18V rails , and you're good

aha ...... I forgot to say - second half JFets - they're having gates clamped to 18V ; source is looking at 1K resistors and they will fight to death to keep source voltage somewhere near 18V too

think how JFet is biased and you'll realize what "somewhere" means

 

[vdi_nenna]

Man, this stuff is confusing. More power to you guys.