Power amp under development

Jump to Latest
#3,242
Hi

I want say thank you to quasi for ideas and design....


I want add my ideas in Nmos for powerful audiophil Pa amplifier and share experience with all people which interested to build

I have update schematic and finished PCB today

@andrewlebon

please send me email


does anybody have idea to improve or find any faults in design ?


I cant upload PCB design to share because its to big, if somebody interest email me
 

Attachments

#3,243
Hi,
convert the output Thiele Network to a Pi filter.

Add a 8r2 or 10r with a series 47pF cap before the inductor and to ground. Keep this part of the Pi filter very close to the output stage devices and a short route to the power ground.
Try changing R60 & R61 from 10r to 3r9.
This last R+C part of the Pi filter can go across the speaker terminals.
The inductor//resistor can be located where convenient, anywhere between the first part of the Pi and the last part of the Pi.

This is a change from my previous recommendation but, I've not tested it thoroughly yet.

There's something seriously wrong with the protection.
You have an arrangement suited to fully complementary output stage and the sense point from the output line should be from the source of the output FETs.

Are the diode string D12 to D16 and C19 tapped into the correct locations?

What about protection Zeners for the FET gates?
 
#3,244
I'd do it the other way round - RC on amp side, and maybe a smallish cap on output side.

R+C and L//R values can be tuned to make the impedance seen from the amp be load independent at high frequencies with this configuration - without peak or dip at the turnover frequency of the filter.
 
#3,248
try to use MJE340 for 2SD669A, it should work


Resistors: R16 is 2 Watt, power Devices resistors 5W, all another 0,6W


queck your email

I have send you final Beta PCB Layout

I will add today overheat protect


Attachment: upgrade NMOS MKII 130V with additional Short Circuit Protect and Clip Limit


Does anybody find faults in design ?
 

Attachments

#3,249
A few questions...

1. T18 C and E should be swapped. It won't work this way

2. I don't understand your protection circuit around T14 and T15. It seems it is attached to nothing except output and power supply lines. Maybe a simple I (current) limiter should be enough since you are using robust MOSFET output.

3. Did you simulate this circuit, is it stable?
 
#3,250
d669 for T10 is the wrong choice of transistor.
2SD669 is a driver.
You need a transistor that performs well with a low Ic.
Any small signal transistor would do, or a low wattage (To126) VAS or pre-driver, with high hFE and high fT at the operational current of ~4mA, even an SMD sot23 transistor would be better glued to the driver transistor heatsink.

Your protection on the negative rail is copied from a fully complementary output stage.
This is a quasi complementary output stage.
It is completely inappropriate.
 
#3,251
@AndrewT

I have copy protection from BJT quasi complementary Output Stage, I m surprised that it is completely inappropriate with Nmos

look original schematic PDF

against 2SD669 is a driver

ok its true, but I have different BJT PA Amplifier with this device as VBE and its working very stable, why not in NMOS ?

regards

Peter
 

Attachments

#3,256
Hi qsa,

The way you have re-designed the output stage driver has 2 major problems.

1. You have inserted a FET driver stage for the output. This increases your positive rail losses to at least 8 volts (4 volts at the driver stage and 4 volts at the output stage). This is likely to be 10 volts or more under heavy power. The original design loses 4 to 5 volts because of the transistor driver stage and this has attracted some criticism in terms of efficiency.

2. It seems you understand well that FETs are a voltage driven device by including the 10 ohm resistor on the source of the driver FETs T21 & T22. The voltage across this resistor needs to be about 4 volts in order for the output stage to turn on and for some output bias current to be achieved. But in your design this amounts to 400mA of current. The number of FETs you have decided to use indicates rails of +/- 100v or more so the power dissipation of the driver stage will be no less than 80 watts (yes just the driver stage). Add to this the dissipation of the output stage which would be no less than 40 watts and you have 120 watts of dissipation at idle. This is too much unless you have enormous heatsinks meaning an impractical amp. In my design the driver stage sinks about 18mA and it works fine.

Cheers
Q
 
You must log in or register to reply here.
Top Bottom