Power amp design by Zbig with new compensation method

I want to warn a little bit for small signal capacitors to the input transistors. That can rise the input impedance and with that low frequency noise. This curves are for 100u, 10 u and 1u in to a differential pair of BC559 with 1mA. Gain 40dB. It is easy to see that the low frequency noise has doubled for 1u.
It is the same for the input capacitor and the feedback link. 390 ohms in series with both bases and 100k to ground.
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I want to warn a little bit for small signal capacitors to the input transistors. That can rise the input impedance and with that low frequency noise. This curves are for 100u, 10 u and 1u in to a differential pair of BC559 with 1mA. Gain 40dB. It is easy to see that the low frequency noise has doubled for 1u.
It is the same for the input capacitor and the feedback link. 390 ohms in series with both bases and 100k to ground.
View attachment 1431022
This is caused by the input impedance of the bjt input stage. The impedance at the emitter of the bjt can be reflected back to the base.
If you swap the bjt with jfet, you don't see this effect.
Using a big capacitor, such as 47u is not the perfect solution, because a small DC blocking cap from your signal source output stage could nullify all the effort of 47uf easily.
 
I have not tried jfets but OPA 1655 Mosfet and it wants 0,1uF or more.
As i normally use 0,5 uF and 100k is it no problems with that OP. OPA1611 is more as the BC556.

I have double mosfets at home but i have not tried them yet.
I hope for better matching when they are double. It is a pain to match SMD transistors for me although i use the big SOT23.
 
Of course. Only MJE are added on schematics, no other files are required. To change .tran frequency please change .param frq value, which will set also .four frequency.
If you want to show good FFT graph, increase number of cycles in 'stop time' parameter from 5 into bigger value, e.g. 50 or 100. You may also increase maximum time step walue (divider exponent) from 14 into 15 or 16 to produce more samples - both changes will increase analyze time, so be patient and have a cup of coffee 😉.

Are you going to build one and see...
With parts selected for this design it is possible to order PCB with almost complete smd assembly, even with matched input transistors 🙂. it's a tempting proposal...
 

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I'd like to present my project of power amplifier with novelty (I hope) gain-frequency compensation, and some other tricks resulting with high amplifier gain and very low THD.

Everybody knows most common method of making amplifier stable – it is Miller compensation: capacitor put between output and inverting input of amplifier (across one or more of amplifier’s stages). This simply puts dominant pole at very low frequency producing well known phase-amplitude open loop response of the amplifier, when high gain is flat to frequencies at most hundreds of Hertz (first, dominant pole), and then fall monotonically in 6dB per octave till unity gain.

My solution allows for very high and almost flat gain till almost 1 kilohertz, and then steep but controlled slope and phase till unity gain, where phase margin is above 45 degrees, and Nyquist stability criteria is fully met, even with capacitive load.
Compensation is done by a low pass filter between amplifier's stages with one pole and one zero. This is enough to make amplifier stable, but to increase phase margin I've added small forward compensation and also small Miller compensation with pole beyond low pass filter and zero before unity gain.
All amplifier design is kept as simple as possible, without unnecessary items (like mosfet drivers). I've only left resistors in MOSFET's sources, but only for further shortcut/overcurrent protection.

Finally I’ve got these numbers:

100W 8 Ohm.
115dB maximum open loop gain (with feedback network, amplifier alone has 147dB gain), first pole at 800Hz
111dB gain at 1kHz
92dB gain at 10kHz
Closed loop gain 32dB (40V/V)
Slew rate 47V/us
10MHz
unity gain, with phase margin 62 degree and amplitude margin 10dB
1W 1kHz THD=0,000007%
100W 1kHz THD=0.000035%
Thermal stability (-12% quiescent current at 150 degree Celsius)

NOTE: this is so far LTSpice simulation, but I’ve choosen pats which are cheap, still in production and available everywhere. I’m going to make this amplifier and test it.

Here are some pictures,
Phase-amplitude characteristics
View attachment 1429234
And this same with capacitive load
View attachment 1429235

THD numbers for 1W 1kHz
View attachment 1429236
Fourier for 1kHz 1W
View attachment 1429237
Intermodulation FFT (9kHz+10kHz 8Vpp out)
View attachment 1429238
LTspice do not shows much, so I've put numbers to Excel and produce more legible graph (horizontally kilohertz, vertically dB)
View attachment 1429240
Step response with overdrive. As you see it lasts less than microsecond to stabilize output level
View attachment 1429242
This same step but with input low pass filter (no overdrive with full power 10kHz square wave)
View attachment 1429245
Noise figure
View attachment 1429246
Thermal stability

View attachment 1429247
And finally schematics
View attachment 1429249
This is not a final version, and some improvements should be done, e.g. increase clipping output voltage, and gate protection.
Very interesting sir i like it good work👍🏻
 
This .asc works after downolad, so file is OK. but I've push LTSpice into limits with this design :-(. What is stated in log (Ctrl+L)?
What version of LTSpice dou you use? Mine is 24.1.4 (x64).
You may also try to increase R12 into 100 Ohms, it may help. Sometimes LTSpice fails with complex design, and show strange results.
 
This is not this case. Amp has two power voltages, and output voltage may be as low as -40V where negative VAS rail has -50V, so no lock will occur.
But anyway, such diodes may help LTSpice to calculate proper DC values.
 
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