It could be that there are several bias points, the simulator then more or less randomly ends up in one.
The subcircuit around Q18 and Q19 on itself can have three bias points if R26 is big enough for it to work as a latch, two stable bias points and a metastable point where everything is in balance. I would expect the overall loop to ensure it always goes to and stays in the balanced state, though.
If there should be more than one stable bias point, you definitely have to get rid of the undesired ones before connecting any expensive loudspeakers.
The subcircuit around Q18 and Q19 on itself can have three bias points if R26 is big enough for it to work as a latch, two stable bias points and a metastable point where everything is in balance. I would expect the overall loop to ensure it always goes to and stays in the balanced state, though.
If there should be more than one stable bias point, you definitely have to get rid of the undesired ones before connecting any expensive loudspeakers.
Last edited:
Yes, in general it is in bi-stable flip-flop configuration, and everything depends on R26. Proposed value (500) is low enough to keep it stable. Anyway, R26 is added only to show that gain can be further increased that way. First proposal was without it, and its value may be set to 1m, where whole circuit acts as high impedance load, without any potential instability.
But even with simple resistors, LTSpice sometimes cannot solve diagram even with smal change of elements value (e.g. during .step evaluation).
But even with simple resistors, LTSpice sometimes cannot solve diagram even with smal change of elements value (e.g. during .step evaluation).
The question is always when a simulator ends up in an undesired bias point: is this DC solution physically possible, and if so, could it be stable?
Sometimes saturating transistors or subcircuits that run out of current can lead to bias points that meet both of these criteria and that therefore need to be solved. Other times, depending on the simulator, convergence issues may lead to DC points that don't even meet the Kirchhoff laws and that are therefore plain nonsense.
Sometimes saturating transistors or subcircuits that run out of current can lead to bias points that meet both of these criteria and that therefore need to be solved. Other times, depending on the simulator, convergence issues may lead to DC points that don't even meet the Kirchhoff laws and that are therefore plain nonsense.
It’s probably some minute difference between versions that makes it pick a different bias point.
It is like that. strange DC results like -10mA reverse collector-base current without junction break contition (low Ucb voltage)
Same here, worked without a problem 🙂
@Zbig, is there a way to show the harmonics in FFT like a sloping grasses in the field, I mean yours looks wider from each harmonics.
I already have .option noopiter set
For better FFT it is needed to gather more samples for FFT. Open "Configure anlysis" dialog box from simulate menu,
and you'll find these settings for Transient analysis:
Stop time: {5/frq} - analysis will stop after 5 cycles of frequency given by ".param frq=1kHz"
Time to start saving data: {1/frq} - ignore first cycle, which may have some spikes at the beginning.
maximum timestep: {1/{frq}/2**14} - interval between samples
So with these settings LTSpice will show (5-1)=4 cycles in graph, and make 2^14 (16384) saples in each cycle for FFT graph
For better FFT increase number of cycles in "Stop time", replacing 5 with 51 or 101 (or any number you like),
and also you may increase number of samples replacing power exponent 14 with 15 or 16 in 'maximum timestep'
This will produce enough samples to make FFT more precise and narrower.
When opening FFT you may change number of samples to get best balance between harmonics spikes and "noise" floor (caused mainly by limitted math accuracy). But do not set too low values, because it will also limit upper frequency of the graph and make floor too high, which may obscure smaller harmonics.
Be patient, high number of cycles/samples requires a lot of time to complete calculations
For better FFT it is needed to gather more samples for FFT. Open "Configure anlysis" dialog box from simulate menu,
and you'll find these settings for Transient analysis:
Stop time: {5/frq} - analysis will stop after 5 cycles of frequency given by ".param frq=1kHz"
Time to start saving data: {1/frq} - ignore first cycle, which may have some spikes at the beginning.
maximum timestep: {1/{frq}/2**14} - interval between samples
So with these settings LTSpice will show (5-1)=4 cycles in graph, and make 2^14 (16384) saples in each cycle for FFT graph
For better FFT increase number of cycles in "Stop time", replacing 5 with 51 or 101 (or any number you like),
and also you may increase number of samples replacing power exponent 14 with 15 or 16 in 'maximum timestep'
This will produce enough samples to make FFT more precise and narrower.
When opening FFT you may change number of samples to get best balance between harmonics spikes and "noise" floor (caused mainly by limitted math accuracy). But do not set too low values, because it will also limit upper frequency of the graph and make floor too high, which may obscure smaller harmonics.
Be patient, high number of cycles/samples requires a lot of time to complete calculations
Last edited:
IMO build-in FFT graph is good only for TIM distortion, when you want to see all products of two adjacent freqiecies.
For harmonics of single frequency there are all numeric values in log file, without any in-between floor fluctuations,
so for clean graph simply copy all fourier data into excell, and make 'stock grap' in excel, setting minimum values little below lowest value from log file (it may be done macro).
For harmonics of single frequency there are all numeric values in log file, without any in-between floor fluctuations,
so for clean graph simply copy all fourier data into excell, and make 'stock grap' in excel, setting minimum values little below lowest value from log file (it may be done macro).