Leach went through many revisions of the frequency compensation, and none were very satisfactory (IMO).
Ed
Indeed. Nowadays we are lucky with circuit simulators which do a good job of determining loop gain/phase characteristics which for the most part are pretty accurate.
I want to warn a little bit for small signal capacitors to the input transistors. That can rise the input impedance and with that low frequency noise. This curves are for 100u, 10 u and 1u in to a differential pair of BC559 with 1mA. Gain 40dB. It is easy to see that the low frequency noise has doubled for 1u.
It is the same for the input capacitor and the feedback link. 390 ohms in series with both bases and 100k to ground.
It is the same for the input capacitor and the feedback link. 390 ohms in series with both bases and 100k to ground.
As you can see both input and feedback capacitors are 47 uF, so your comment is a bit out of place.
This is caused by the input impedance of the bjt input stage. The impedance at the emitter of the bjt can be reflected back to the base.
If you swap the bjt with jfet, you don't see this effect.
Using a big capacitor, such as 47u is not the perfect solution, because a small DC blocking cap from your signal source output stage could nullify all the effort of 47uf easily.
I have not tried jfets but OPA 1655 Mosfet and it wants 0,1uF or more.
As i normally use 0,5 uF and 100k is it no problems with that OP. OPA1611 is more as the BC556.
I have double mosfets at home but i have not tried them yet.
I hope for better matching when they are double. It is a pain to match SMD transistors for me although i use the big SOT23.
As i normally use 0,5 uF and 100k is it no problems with that OP. OPA1611 is more as the BC556.
I have double mosfets at home but i have not tried them yet.
I hope for better matching when they are double. It is a pain to match SMD transistors for me although i use the big SOT23.
Nexperia produces also temperature compensated pairs in single SMD package: BCM856BS (2xPNP = BC856B), and BCM846B (2xNPN = BC846B)
with 5% hfe and 2mV Ube tolerance, so it is no problem at all.
Dear Zbig,
please post your .asc file along with any special models you use for us to try as a learning exercise.
please post your .asc file along with any special models you use for us to try as a learning exercise.
Of course. Only MJE are added on schematics, no other files are required. To change .tran frequency please change .param frq value, which will set also .four frequency.
If you want to show good FFT graph, increase number of cycles in 'stop time' parameter from 5 into bigger value, e.g. 50 or 100. You may also increase maximum time step walue (divider exponent) from 14 into 15 or 16 to produce more samples - both changes will increase analyze time, so be patient and have a cup of coffee 😉.
If you want to show good FFT graph, increase number of cycles in 'stop time' parameter from 5 into bigger value, e.g. 50 or 100. You may also increase maximum time step walue (divider exponent) from 14 into 15 or 16 to produce more samples - both changes will increase analyze time, so be patient and have a cup of coffee 😉.
With parts selected for this design it is possible to order PCB with almost complete smd assembly, even with matched input transistors 🙂. it's a tempting proposal...
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This .asc works after downolad, so file is OK. but I've push LTSpice into limits with this design :-(. What is stated in log (Ctrl+L)?
What version of LTSpice dou you use? Mine is 24.1.4 (x64).
You may also try to increase R12 into 100 Ohms, it may help. Sometimes LTSpice fails with complex design, and show strange results.
What version of LTSpice dou you use? Mine is 24.1.4 (x64).
You may also try to increase R12 into 100 Ohms, it may help. Sometimes LTSpice fails with complex design, and show strange results.
That might mean the circuit could not establish DC work point. The negative input has to be at least 2 Vbe above the negative rail. Otherwise, the current would be pinched off and output would be stuck at negative rail.
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The solution might be put 2 back-to-back Zener diodes (e.g. 5V) on top of C3 to limit voltage swing.
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