Steve,
I owe you an apology.
I now see what you mean by clamping diodes; I had thought you meant beefy diodes across the CE of each output bipolar; it seems you mean back to back zeners across GS on a mosfet.
My apologies, Effendi...... Slipshod reading of me! 😕
As it happens, I do agree with you. Such diodes are, in my belief, mandatory, as I've broken quite a few mosfets with spikes to the gate.
Cheers,
Hugh
I owe you an apology.
I now see what you mean by clamping diodes; I had thought you meant beefy diodes across the CE of each output bipolar; it seems you mean back to back zeners across GS on a mosfet.
My apologies, Effendi...... Slipshod reading of me! 😕
As it happens, I do agree with you. Such diodes are, in my belief, mandatory, as I've broken quite a few mosfets with spikes to the gate.
Cheers,
Hugh
AKSA said:
Fer shame! 🙂
Actually I believe what Fred's talking about isn't diodes to protect the gate from ESD, but rather to keep the gate-to-source voltage from reaching the gate-to-source breakdown voltage which is usually relatively low at around 20 volts.
He's worried that signal overshoot resulting from the allegedly undamped resonance formed by the transformer's secondary leakage inductance and the MOSFET's input capacitance could exceed the gate-to-source breakdown voltage causing failure.
In other words something like a high level transient signal at the input from something like a drum thwack.
Though given that this is a source follower I'm not sure I see how that would be problematic in this particular circuit.
The output's taken from the source and since in a follower your output voltage is just slightly less than your input voltage and of the same polarity the gate-to-source voltage isn't going to change appreciably and won't go anywhere near the gate-to-source breakdown voltage.
Now for a common source amplifier powered by a single supply I can see where this would be a problem because the source is typically tied to ground so the gate-to-source voltage is effectively your input voltage therefore if your input voltage exceeds the gate-to-source breakdown voltage, you're screwed.
Protecting the gate from static discharge is a good idea. But in this case the gate is electrically isolated from the input via the input transformer. So you don't have quite the same situation you have in the case of the Son of Zen with its direct coupled input.
se
AKSA said:Steve, why defend your position with such verbal violence? No one is sleeping with your wife, fer crissakes....... No honor has been trampled, no dignity exposed.
The verbal violence isn't to defend my position. The verbal violence is due to something of a weakness of mine. If someone kicks me in the shins, I kick back.
Fred's pretty much incapable of respectfully disagreeing with someone and presenting a mature and cogent argument. Instead he disagrees by way of ridicule and mockery. So when I respond to him I afford him no more respect than than he's shown me.
If someone disagrees with me in a respectful manner, they'll find that I afford them the same respect.
se
SY said:
What sort of noise? You mean noise noise or like cymbal crash noise? If the former, where you gonna get noise of such a magnitude to approach the gate-to-source breakdown voltage?
In any case, with a source follower such as the circuit in question, I don't see how a signal at the input even in excess of the gate-to-source breakdown voltage will necessarily be a problem. I do see it being a problem in a commn source circuit. But this isn't a common source circuit.
se
No, not musical signal; that's slow stuff. And with modern sources, safely bandlimited. I'm speculating that Fred is thinking of stuff like diode switching noise, RF, transients from electrical equipment nearby turning on and off; you know, noise.
SY said:
Ah, ok.
Well, all I can say is that if you've got noise on your input on the order of 20 volts, the lack of any clamping diodes is the least of your problems. 🙂
se
It doesn't need to be that big on the input if it's fast enough. It just needs to have been amplified enough by the time it gets to the source follower. I'm not saying any of this is likely, just that this is the kind of stuff some people worry about.
Then again, I plug my system into the wall, which has to make you a little squeamish. 😉
Then again, I plug my system into the wall, which has to make you a little squeamish. 😉
I never used any of those clamping diodes in all (Nelson Pass) designs that I've built. The amps were loaned to many different people, in many different locations and not a single problem so far.
IRF series. I don't think they have diodes built in, as Nelson recommended using diodes, but also said, that if you are careful you could do without them😉
Zener diodes Z1, Z2, Z3 and Z4
form input protection networks which prevent input voltages in excess of
9 volts or so. Higher values can be used, with 16 volt Zener diodes
being the practical limit. It is not essential that the input protection
diodes be used, but without them greater care will be necessary in
connecting signal sources.
Zener diodes Z1, Z2, Z3 and Z4
form input protection networks which prevent input voltages in excess of
9 volts or so. Higher values can be used, with 16 volt Zener diodes
being the practical limit. It is not essential that the input protection
diodes be used, but without them greater care will be necessary in
connecting signal sources.
Re: Re: Fools Rush In Where Angels Fear to Tread
This was also my impression after reading the thread. I truly can't understand, why all this argument really took place. Can we concentrate on 1 transistor clapping again? The weekend is almost over😉
Steve Eddy said:
This was also my impression after reading the thread. I truly can't understand, why all this argument really took place. Can we concentrate on 1 transistor clapping again? The weekend is almost over😉
fdegrove said:
Having had the pleasure of several talks with Mr Hiraga on audio design, including my own design, let me tell you that as much as he is editor and writer, he IS a designer! The insight he has in circuitry and the issues that influence sound quality, as demonstrated again and again by his own designs can put many so-called designers to shame.
The original Nemesis is a commercial product (can still be found) and works very well thank you. The fact that people bastardize Mr Hiraga's design with less success doen't say a lot about the original design.
Jan Didden
Peter Daniel said:
Yup. Basically you want to protect from ESD which isn't much of an issue when the gate's electrically isolated from the input.
se
where even fools fear to tread.........
"IRF series. I don't think they have diodes built in, as Nelson recommended using diodes, but also said, that if you are careful you could do without them"
"Yup. Basically you want to protect from ESD which isn't much of an issue when the gate's electrically isolated from the input."
Not on an undamped transformer driving circuit a capacitive input source follower circuit and at large votage swings.
An ESD event is a high edge rate waveform that can be coupled though interwinding capacitance to the gate of the mosfet.
Input transients to the step transformer
with no intentionly designed damping and zener gate clamps will very likely cause overshoots and/or ringing that is very likely to damage the transistor.
If you guys have no experience or understanding resonant (RCL) circuits and mosfet failure modes, be quiet. You guys are offering "advice" that will lead to very possible amplifier failure and speaker damage for those who might think you are serious, rather than just posting idle speculations on something that you have no plans to reseach much less build, test, and measure.
I worked on protection circuits including those involving inductive loads and ESD for two years for an international telecom company.
Your actual experience or qualification would be what exactly?
"IRF series. I don't think they have diodes built in, as Nelson recommended using diodes, but also said, that if you are careful you could do without them"
"Yup. Basically you want to protect from ESD which isn't much of an issue when the gate's electrically isolated from the input."
Not on an undamped transformer driving circuit a capacitive input source follower circuit and at large votage swings.
An ESD event is a high edge rate waveform that can be coupled though interwinding capacitance to the gate of the mosfet.
Input transients to the step transformer
with no intentionly designed damping and zener gate clamps will very likely cause overshoots and/or ringing that is very likely to damage the transistor.
If you guys have no experience or understanding resonant (RCL) circuits and mosfet failure modes, be quiet. You guys are offering "advice" that will lead to very possible amplifier failure and speaker damage for those who might think you are serious, rather than just posting idle speculations on something that you have no plans to reseach much less build, test, and measure.
I worked on protection circuits including those involving inductive loads and ESD for two years for an international telecom company.
Your actual experience or qualification would be what exactly?
Re: where even fools fear to tread.........
Where do you keep coming up with this undamped stuff?
If you drive the JT-13K7-A wholly unloaded (i.e. into an open circuit with no external damping much as it would see driving the MOSFET directly), you get just a bit of a resonant peak at about 120kHz due to leakage inductance and winding capacitance. The Q is only about 1.4 so clearly there is a good amount of internal damping.
Sure it's a bit underdamped, but it's not the undamped horror show you keep wanting to portray.
Take another look at the schematic. There's an electrosatic shield between the primary and secondary windings which is tied to ground.
And don't forget about the shunt winding capacitance which provide a low impedance path to ground (which is what limits the transformer's high frequency response).
Ok, let's take a look at this.
All else being equal, the transformer's resonant frequency is at 120kHz. What input signal is going to have a 120kHz component of such a high level that with the overshoot of a relatively low Q resonance is going to show up at the input at a level approaching 20 volts?
I understand resonant RLC circuits. And I understand that if you exceed the MOSFET's gate-to-source breakdown voltage you can cause the device to fail. I can also understand your concerns if what we were talking about here were a MOSFET configured as a common source amplifier.
But this isn't a MOSFET configured as a common source amplifier where the gate-to-source voltage is essentially your input voltage. It's a MOSFET configured as a common drain amplifier where its source is effectively at the same potential as the gate.
So what am I missing here? If the gate's at say, +5 volts with respect to ground then the source will also be at +5 volts with respect to ground. So the gate-to-source voltage will be (+5) - (+5) = 0.
And yes, I know that it won't actually be 0. Just keeping the example simple. Point is, an input signal in excess of the gate-to-source breakdown voltage doesn't result in a gate-to-source voltage anywhere near the breakdown voltage.
If this is not the case, what am I missing?
With your claimed experience and qualifications, you should be able to explain how, in a common drain circuit such as the one in question, if you put say a 20 volt signal at its input that you get a drain-to-source voltage on the order of 20 volts.
I can see how that would be very easy to do with a common source configuration and why one would see clamping diodes as being more a necessity. If the source is grounded, you'd basically just have to apply a 20 volt signal to get a 20 volt gate-to-source voltage.
But as far as I'm aware, this wouldn't be the case with a common drain circuit.
So again, what am I missing?
se
Fred Dieckmann said:
Where do you keep coming up with this undamped stuff?
If you drive the JT-13K7-A wholly unloaded (i.e. into an open circuit with no external damping much as it would see driving the MOSFET directly), you get just a bit of a resonant peak at about 120kHz due to leakage inductance and winding capacitance. The Q is only about 1.4 so clearly there is a good amount of internal damping.
Sure it's a bit underdamped, but it's not the undamped horror show you keep wanting to portray.
Take another look at the schematic. There's an electrosatic shield between the primary and secondary windings which is tied to ground.
And don't forget about the shunt winding capacitance which provide a low impedance path to ground (which is what limits the transformer's high frequency response).
Ok, let's take a look at this.
All else being equal, the transformer's resonant frequency is at 120kHz. What input signal is going to have a 120kHz component of such a high level that with the overshoot of a relatively low Q resonance is going to show up at the input at a level approaching 20 volts?
I understand resonant RLC circuits. And I understand that if you exceed the MOSFET's gate-to-source breakdown voltage you can cause the device to fail. I can also understand your concerns if what we were talking about here were a MOSFET configured as a common source amplifier.
But this isn't a MOSFET configured as a common source amplifier where the gate-to-source voltage is essentially your input voltage. It's a MOSFET configured as a common drain amplifier where its source is effectively at the same potential as the gate.
So what am I missing here? If the gate's at say, +5 volts with respect to ground then the source will also be at +5 volts with respect to ground. So the gate-to-source voltage will be (+5) - (+5) = 0.
And yes, I know that it won't actually be 0. Just keeping the example simple. Point is, an input signal in excess of the gate-to-source breakdown voltage doesn't result in a gate-to-source voltage anywhere near the breakdown voltage.
If this is not the case, what am I missing?
With your claimed experience and qualifications, you should be able to explain how, in a common drain circuit such as the one in question, if you put say a 20 volt signal at its input that you get a drain-to-source voltage on the order of 20 volts.
I can see how that would be very easy to do with a common source configuration and why one would see clamping diodes as being more a necessity. If the source is grounded, you'd basically just have to apply a 20 volt signal to get a 20 volt gate-to-source voltage.
But as far as I'm aware, this wouldn't be the case with a common drain circuit.
So again, what am I missing?
se
stop them at the gate to the castle
Both Jocko and I have been burned by lack of gate stopper resistors, one of these being a case paralleled jfet followers that very occasionally broke into parasitic oscillation and the other being an inverted casode with p and n channel jfets that had a well damped overshoot well above the audio range. This circuit did not oscillate but had a high frequency hardness that became more noticeable as the other circuit development brought more resolution. A gate damping resistor for the cascode jfet got rid of overshoot and the hardness as well adding some transparency. A nice return for a 5 cent resistor. Hugh Dean spoke of using emitter resistors on the upper BJTs in a cascode and I believe it is a similar fix to the same problem I saw (and heard). This is why Jocko and I have so many informal design reviews while eating pizza (that and the fact that I know little about baseball which he gets annoyed trying to explain to me). I have heard stories about Paul Klipsch carrying a pocket notebook around dropping it in the middle of his plate to jot down a circuit before the idea got away. I have no trouble believing them.
The single transistor amplifier approach has been thoroughly examined including the tradeoffs that come from very simple circuits. The gate to source capacitance is very high for a common source topology and is one of the biggest headaches. This topic is examined in Nelson Pass's series of Zen articles and it is well worth reading these again to get a feel for influence of this on the circuit.
The capacitance for a mosfet follower is much less than common source topology, but by adding the step up transformer you increase the effective input capacitance by the square of the turns ratio and have a significantly lower impedance to drive at high frequencies than that looking into the gate of the mosfet follower. To paraphrase the old standard saying: No gain with no pain. Even driving when mosfet followers with tube circuits an intermediate follower is well advised for driving the gate of a high transconductance mosfet (the ones with low output impedance that make really good followers). In engineering there is no free lunch. In high end audio amplifiers the design choices, trade offs, and compromises become complicated enough to start to resemble the political deal making that occurs late at night in smoke filled rooms free from public scrutiny. Not only is there no free lunch, but sometimes there is not even a reasonably priced lunch that you would want to eat. Simple circuits involve a lot of complicated decisions on how to rob Peter to pay Paul for a circuit of reasonable complexity.
Both Jocko and I have been burned by lack of gate stopper resistors, one of these being a case paralleled jfet followers that very occasionally broke into parasitic oscillation and the other being an inverted casode with p and n channel jfets that had a well damped overshoot well above the audio range. This circuit did not oscillate but had a high frequency hardness that became more noticeable as the other circuit development brought more resolution. A gate damping resistor for the cascode jfet got rid of overshoot and the hardness as well adding some transparency. A nice return for a 5 cent resistor. Hugh Dean spoke of using emitter resistors on the upper BJTs in a cascode and I believe it is a similar fix to the same problem I saw (and heard). This is why Jocko and I have so many informal design reviews while eating pizza (that and the fact that I know little about baseball which he gets annoyed trying to explain to me). I have heard stories about Paul Klipsch carrying a pocket notebook around dropping it in the middle of his plate to jot down a circuit before the idea got away. I have no trouble believing them.
The single transistor amplifier approach has been thoroughly examined including the tradeoffs that come from very simple circuits. The gate to source capacitance is very high for a common source topology and is one of the biggest headaches. This topic is examined in Nelson Pass's series of Zen articles and it is well worth reading these again to get a feel for influence of this on the circuit.
The capacitance for a mosfet follower is much less than common source topology, but by adding the step up transformer you increase the effective input capacitance by the square of the turns ratio and have a significantly lower impedance to drive at high frequencies than that looking into the gate of the mosfet follower. To paraphrase the old standard saying: No gain with no pain. Even driving when mosfet followers with tube circuits an intermediate follower is well advised for driving the gate of a high transconductance mosfet (the ones with low output impedance that make really good followers). In engineering there is no free lunch. In high end audio amplifiers the design choices, trade offs, and compromises become complicated enough to start to resemble the political deal making that occurs late at night in smoke filled rooms free from public scrutiny. Not only is there no free lunch, but sometimes there is not even a reasonably priced lunch that you would want to eat. Simple circuits involve a lot of complicated decisions on how to rob Peter to pay Paul for a circuit of reasonable complexity.
Re: stop them at the gate to the castle
Question. If the overshoot was well above the audio range, how was it that it was problematic? Unless you're feeding it a signal at that frequency, what is there to overshoot?
Anyway, as I pointed out previously, the transformer in question has a very low Q resonance when completely unloaded.
Sure. But so what? I never said there were no caveats involved here. I just don't see that the circuit as-drawn is the horrid danger you've been making it out to be.
Never said there was any free lunch. And I'm well aware of the inherent limitations of the circuit. But if you want as much linearity as possible with as few components as possible and just a single active device, I see no reason why this won't fit the bill if you're willing to accommodate those limitations. And that pretty much just boils down to avoiding driving it with tubes or passive attenuators.
se
Fred Dieckmann said:
Question. If the overshoot was well above the audio range, how was it that it was problematic? Unless you're feeding it a signal at that frequency, what is there to overshoot?
Anyway, as I pointed out previously, the transformer in question has a very low Q resonance when completely unloaded.
Sure. But so what? I never said there were no caveats involved here. I just don't see that the circuit as-drawn is the horrid danger you've been making it out to be.
Never said there was any free lunch. And I'm well aware of the inherent limitations of the circuit. But if you want as much linearity as possible with as few components as possible and just a single active device, I see no reason why this won't fit the bill if you're willing to accommodate those limitations. And that pretty much just boils down to avoiding driving it with tubes or passive attenuators.
se
more than anyone wants to know
I am going to assume are asking in non sarcastic manner and I will reply in kind.
ESD events are very fast RF waveforms there is capacitive coupling between the primary winding and electrostatic shield and capacitive coupling between the same shield and the secondary winding. This looks like two capacitors in series. The electrostatic shield will also be connected to the earth ground through an inductive impedance from PCB traces and wiring. During testing of telecom boards, I had ESD events (which are up to several thousand volts) develop enough ground bounce across a wide 12" long PCB trace connected to an excellent ground plane in the system's back plane, to reset the CMOS logic and fail the regulatory requirements for ESD immunity. We had to use spring clips mounted within an inch of card's front panel and which contacted the aluminum card cage in which the board was inserted. The series inductance for the card cage to earth ground was much lower due to the much larger surface area and multiple paths to earth ground. I am not going to tell you that I am an expert EMI or RF designer but I read several of the industry standard reference books and received help in this subject from Pete Goudreau who is definitely an expert. Interwinding capacitance and leakage inductance are distributed impedances. The capacitive coupling between each turn as well as the inductive and resistive properties of the length of wire are a much more complicated circuit than the lumped sum models. You just cannot think of the high frequency parasitics as single element lumped capacitors and inductors. The coupling does not even have to be that good since you can attenuate the ESD voltage by a couple of orders of magnitude and still have several 10s of volts at the gate of the mosfet. Rrsonance of gate capacitance and transformer and/or wiring inductance which usually occurs at RF frequencies. At these frequencies where this simplified model for the transformer falls apart, prediction from a model, seems to be to be a fruitless task.
I am going to assume are asking in non sarcastic manner and I will reply in kind.
ESD events are very fast RF waveforms there is capacitive coupling between the primary winding and electrostatic shield and capacitive coupling between the same shield and the secondary winding. This looks like two capacitors in series. The electrostatic shield will also be connected to the earth ground through an inductive impedance from PCB traces and wiring. During testing of telecom boards, I had ESD events (which are up to several thousand volts) develop enough ground bounce across a wide 12" long PCB trace connected to an excellent ground plane in the system's back plane, to reset the CMOS logic and fail the regulatory requirements for ESD immunity. We had to use spring clips mounted within an inch of card's front panel and which contacted the aluminum card cage in which the board was inserted. The series inductance for the card cage to earth ground was much lower due to the much larger surface area and multiple paths to earth ground. I am not going to tell you that I am an expert EMI or RF designer but I read several of the industry standard reference books and received help in this subject from Pete Goudreau who is definitely an expert. Interwinding capacitance and leakage inductance are distributed impedances. The capacitive coupling between each turn as well as the inductive and resistive properties of the length of wire are a much more complicated circuit than the lumped sum models. You just cannot think of the high frequency parasitics as single element lumped capacitors and inductors. The coupling does not even have to be that good since you can attenuate the ESD voltage by a couple of orders of magnitude and still have several 10s of volts at the gate of the mosfet. Rrsonance of gate capacitance and transformer and/or wiring inductance which usually occurs at RF frequencies. At these frequencies where this simplified model for the transformer falls apart, prediction from a model, seems to be to be a fruitless task.
Attachments
Hi,
Have all the fun you like, just don't expect any of us to take you seriously.
BTW, how do you make your own quotes from other members?
Taking snippetts of text of mine is O.K by me, adding lines of your own isn't really kosher, is it?
Cheers and keep scratching,😉
Have all the fun you like, just don't expect any of us to take you seriously.
BTW, how do you make your own quotes from other members?
Taking snippetts of text of mine is O.K by me, adding lines of your own isn't really kosher, is it?
Cheers and keep scratching,😉
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