Open loop gain, phase margin etc

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#23
You might want to take a closer look at Q20...
Click to expand...

He he, ooops! For some reason Orcad always places PNP transistors upside down, must have forgot to swap that one.

Adding a resistor in series with C3 doesn't have the desired response. It makes the peak sharper but doesn't reduce the amplitude.

Regarding the high frequency square waves, it just sent the amp into oscillation. I didn't let it do it long enough to measure the frequency but it was quite high, definitely in the MHz region.
 
#24
i'm thinking that 22p integrating cap might be the reason for the peak at 10Mhz. there is a point where the phase shift of the amp and the phase shift of integrating caps add to 180 degrees. that's one reason i try to stay away from integrating caps as a solution to instability. there is a point where the phase shift of the integrating cap becomes a liability.
 
#25
Having a bit of a play around, I've found that if I put the Miller cap around just Q8 rather than the whole Q8/9 CFP VAS transistor the situation is improved slightly. The roll-off has smoothed out a bit but I'm still getting only a few dB of gain margin. How much gain margin is normal?

I've also moved the integration network (now an 47pF in series with 1k resistor) to the VAS output rather than the main amplifier output.

Latest bode plot: http://www.chaudio.co.uk/AmpDesign/TestAmp2Bode3.pdf

Looking back at the bode plot for the VAS stage on it's own, it would suggest that the output stage is upsetting things. I do like that output stage arrangement and I know of at least one commercial amp which uses it successfully but maybe there are better options. I've been going through all of the possible permutations in my head but of course all have their pros and cons.

Given the initial application for this amp I could probably get away with only a two stage output, either EF or CFP but I like the extra current gain you get from the triple and it minimises the load on the VAS.
 
#26
Ok, here's a question I can't figure out:

Why does adding VAS degeneration add extra phase shift and screw up the phase margin?

Whatever I've tried, I can't get the gain margin above 10dB, even if the phase margin is 90deg.

Edit: Changing to a fairly standard EF triple improves things but only slightly. Phase margin just over 90deg, gain margin 9dB.
 
#27
how are you "measuring" gain/phase margin in your sim?

the "simple Middlebrook" method has problems when parasitic C causes signal feed thru or loading effects complicate loop transmision calculation

for a step up in accuracy search for "loop gain probe" + "Tain" - free LtSpice has example files

(both shown earlier bybuleskynis)

Middlebrook's "final solution" is his GFT tools which IntuSoft has app notes on and the LtSpice Yahoo users group has LtSpice example files
 
#29
There's some discussion of this over in the SPICE thread starting here. The quantity you want to simulate for stability analysis is not the closed-loop gain but the "loop gain" AOLB - that is, the product of the open-loop gain of the amplifier and the feedback factor, taking impedance interactions between the feedback network and amplier into account.

What simulator are you using?
 
#30
Ok, cheers Andy, I think I'm starting to understand. I really should know all of this already but I don't remember enough from my courses at uni and they never actually taught how to look at real world problems. There are so many gaps in my knowledge. I really should re-learn S plane and stability analysis.

I'm using Orcad/PSpice.
 
#33
Has anyone else tried using Jim Thomsons loop gain probe?

I've inserted it into my circuit but when I run the simulation I get an invalid command error. I don't know enough about PSpice to debug it.

The output I get is:

Code: 
.subckt SCHEMATIC1_U1 pin1 pin2   ******************                   * LOOPGAIN CHECKER           .PARAM PASS=0           .STEP PARAM PASS LIST 0 1  ---------$ ERROR -- Command invalid in subcircuit          IMAC 0 LG AC {PASS}           VMAC LG pin1 AC {1-PASS}           VDUMU1 LG pin2 0           ******************           ** Copyright by James E. Thompson, 1994-2005  **           ****************** .ends SCHEMATIC1_U1

That didn't work well how about:


.subckt SCHEMATIC1_U1 pin1 pin2
******************
* LOOPGAIN CHECKER
.PARAM PASS=0
.STEP PARAM PASS LIST 0 1
---------$
ERROR -- Command invalid in subcircuit
IMAC 0 LG AC {PASS}
VMAC LG pin1 AC {1-PASS}
VDUMU1 LG pin2 0
******************
** Copyright by James E. Thompson, 1994-2005 **
******************
.ends SCHEMATIC1_U1
 
#34
ceharden said:
Ok, here's a question I can't figure out:

Why does adding VAS degeneration add extra phase shift and screw up the phase margin?

Whatever I've tried, I can't get the gain margin above 10dB, even if the phase margin is 90deg.
Click to expand...


Is this with standard Miller compensation?

If so;

At HF, when the VAS is operating with 100% negative feedback (Cdom = short circuit) the impedance looking into the base will be (approximately) equal to the emitter resistance. In other words, the higher the emitter degeneration applied to the VAS, the greater the minimum input impedance.
The voltage gain of the VAS will be unity and the voltage gain of the LTP will be equal to the input impedance of the VAS / the gm of the LTP. At this point, Cdom cannot reduce the open loop gain of the amplifier any further.

If the gm of the LTP is great enough (compared to the minimum input impedance of the VAS), it is possible that the open loop gain may plateau at a value close to the closed loop gain. If this is the case then you will never get an adequate gain margin for stability, even if you make Cdom 100nF.

This is a danger of applying excessive emitter degeneration to the VAS.
 
#35
btw.... having had a little more time to look at your bode plot, i began wondering..... what is the scaling of the plot? is it dbV?, if so, you're amp is actually stable, since your input signal is 1V (0dbv) and your gain drops below 1 before any real phase phunnies start to occur (pardon the pun, i was just having some "phun" with the phrase.....)

the steep slope after the phase shift point would certainly be a sign of instability if it happened with any gain. if you read any literature on amp stability, the 2 signs in a bode plot of instability are 1) a peak in the response curve, and 2) a 20db/decade slope (instead of a 10db/decade slope). your phase margin seems to be about 80 degrees at 0dbv, which is actually pretty good. the slope shows some effects from the beginning of the phase shift change, but it shouldn't cause a problem..... you circuit sims great, but the actual physical model has other capacitances and inductances that don't show up in most models. you might want to look at board layout and wiring layout. also i notice you don't have a zobel network or damped inductor in your output circuit. the zobel network shunts low level oscillations to ground, and the inductor isolates the amplifier from load capacitances (load capacitance contributes to instability).
 
#36
Thanks for those replies, very useful indeed. The VAS degeneration causing the open-loop gain to plateau makes a lot of sense from some of the things I've seen in simulation.

My main reasons for wanting the degeneration were to actually reduce the gain of the whole circuit because I thought it was quite high to control just with global NFB and also to produce a slight voltage shift to match the voltage across the current mirror and it's degeneration resistors.

The scale is indeed in dBV, I'm used to looking at Bode plots with logarithmic scales, makes more sense to me. Thanks for the vote of confidence with the design. I don't think I was too far off with the one I built but going through this process has taught me a lot of little things to watch for.

I'm aware of Zobel networks but I don't see the point in putting one in the simulations unless I start modelling speakers as loads, which I might at some point. I should have put one on the prototype but never got round to it!

Next job is to deal with thermal stability!


There's probably still room for some component value tweaks but I think I've got the topology close enough to be able to design a PCB first. I'm going to try an keep things as neat and as logical as possible. Not like a commercial amp I saw recently where the Zobel network shared a ground trace with the input stage!!! Strangely enough it has a bit of an oscillation problem!
 
#37
i've seen a lot of commercial designs where i've seen something like that, and i say "what were you thinking?". like well designed circuits, and even well laid out amp boards, but they run one of the rail voltage lines to the outputs riight past the input stage. the top of my "STOOOPID" list is new receivers that have "puzzle boxes" of circuit boards in them, and you can't get at the output stages to troubleshoot them without disassembling the "puzzle". and better still (actually worse), is the manufacturer who put a bunch (about 8 of them) of 3 terminal regulators down in a space at the bottom of the puzzle box (completely boxed in of course), and none of them heat sinked, just free standing, and at least 3 of them with direct 32V inputs (they're rated 35V input max). needless to say, about 80% of the problems with this particular series (not just a single model) of receivers is these regulators failing.
 
#40
Why put the capacitor 22pF short circuit ratio? was necessary
Click to expand...

I'm sorry, I don't understand the question. On my latest revision, the 22pF is replaced with a 47pF with a 1k resistor in series. The purpose of it is to further reduce the HF response but without using a huge miller cap.

See latest schematic: http://www.chaudio.co.uk/AmpDesign/TestAmp2Sch3.pdf

I have been doing simulations without the input capacitor. The problem is, do I post the schematic of exactly what I'm simulating, or of a real useable amplifier?

As an amp repairer I see lots of really bad designs! I understand how to make an existing design work and a lot of what not to do. What I'm trying to learn is how to arrive with that design in the first place, choosing component values etc.
 
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