THX, Eva.
I actually found your schematic of "magnetic snubber" on one of your PFC schematics.
To me, it's a flyback converter for capturing the energy caused by reverse recovery current of the boost rectifier and returning it to the output. The flyback is in turn snubbed by RC network.
It works alright. I just didn't come across that name before.
I actually found your schematic of "magnetic snubber" on one of your PFC schematics.
To me, it's a flyback converter for capturing the energy caused by reverse recovery current of the boost rectifier and returning it to the output. The flyback is in turn snubbed by RC network.
It works alright. I just didn't come across that name before.
Theoretically it should also be possible to use the output filter itself "to snub" but one would have to be careful not to increase THD this way.
Peavey used such a contraption within their 80ies DECA series. The original idea came from Brian Attwood.
Regards
Charles
Peavey used such a contraption within their 80ies DECA series. The original idea came from Brian Attwood.
Regards
Charles
Eva, Charles,
do you mean something like the attached schematic?
I was thinking of such a solution, but did not like the requirement of additional freewheeling diodes.
In any case I think will have to play around with the switching behaviour of my IRFB52N15D in order to get a rough idea about their behaviour, before jumping into the complete bridge circuit.
Back to topic:
The new chip is looking quite interesting from point of view. It mostly the perfect match, what I was looking for. Let's see if I can get some and how they do the job in real life.
IRS20954S seems to be available from the IR website. Registered users can order them by credit card.
Roughly 4 USD per piece + shipping/handling. Depending on where you live... shipping/handling can be expensive...
P.S. Eva:
Hope the customer likes your SMPS!
... I am right now optimizing my 1kW boost .
It can deliver 1kW at input voltages down to 160V / AC, for short term at 230V roughly 1.4KW. At 120V it is still above 700W.
...peak currents in the choke are around 20A and the fast MosFets turn this off with 30ns... means every nH in the layout generates a peak of roughly 600mV-700mV...
...handling 666A/us is tough... my silly USB scope tends to hang up frequently due to the fast transients when measuring at the MosFet shunts....
do you mean something like the attached schematic?
I was thinking of such a solution, but did not like the requirement of additional freewheeling diodes.
In any case I think will have to play around with the switching behaviour of my IRFB52N15D in order to get a rough idea about their behaviour, before jumping into the complete bridge circuit.
Back to topic:
The new chip is looking quite interesting from point of view. It mostly the perfect match, what I was looking for. Let's see if I can get some and how they do the job in real life.
IRS20954S seems to be available from the IR website. Registered users can order them by credit card.
Roughly 4 USD per piece + shipping/handling. Depending on where you live... shipping/handling can be expensive...
P.S. Eva:
Hope the customer likes your SMPS!
... I am right now optimizing my 1kW boost .
It can deliver 1kW at input voltages down to 160V / AC, for short term at 230V roughly 1.4KW. At 120V it is still above 700W.
...peak currents in the choke are around 20A and the fast MosFets turn this off with 30ns... means every nH in the layout generates a peak of roughly 600mV-700mV...
...handling 666A/us is tough... my silly USB scope tends to hang up frequently due to the fast transients when measuring at the MosFet shunts....Regarding the original topic: It is interesting that it took them so long to bring out this chip. Years ago I stumbled over an IRF patent on a driver like that. I then immediately emailed them to ask when they would bring out such a chip. They said that they wouldn't know since there wasn't enough demand fo it back then.
Regards
Charles
Regards
Charles
why cannot they take it one-step further and integrate the front end into it so that they have an all-in solution? it shouldn't be that complicated - see those synchronous buck converters.
It seems to me that doing so would limite the scope of the chip to maybe just a few particular designs.
What I'd like to see is predictive deadtime implemented.
What I'd like to see is predictive deadtime implemented.
classd4sure said:
Agreed - on both counts. Not only would adding in a particular analog front end be limiting the IC's general applicability, but the IC design drivers for isolated well MOSFET digital (mostly) circuitry and low level, low offset, low noise input circuitry are somewhat at odds. I suppose they might be able to put in a reasonable comparator with the two extra pins, but it would add to the cost and probably wouldn't be of high enough audio grade performance (the HP408? with the built-in comparator suffered this way).
Servoed, predictive deadtime would be very nice, but I don't think a good scheme for this yet exists in discrete form (let alone an IC). One nice bit of news, compared to the previous, similar IC, IR has greatly tightened up the timing tolerance in the deadtime generator.
Regards -- analogspiceman
PS: I've went ahead and made up an LTspice model for this part, but I'm not quite ready to post it. I had to guess at a several performance characteristics and have an unanswered email request in with IR for more detailed info.
What are your thoughts on TI's "digital" scheme of predictive dead time? I think I'd much prefer an analog one but it seems like it could work? THey've only got it rated up to 500kHz though, and at very low voltage.
I don't know how one would go about a servo type control. I believe it would have to be triggered by the di/dt at the output. Some sort of charge balancing/locked loop. The hard part would be to make it fast enough to actually be useful, and secondly simple enough to actually be doable.
Looking forward to your new model though, another fine contribution from you.
I don't know how one would go about a servo type control. I believe it would have to be triggered by the di/dt at the output. Some sort of charge balancing/locked loop. The hard part would be to make it fast enough to actually be useful, and secondly simple enough to actually be doable.
Looking forward to your new model though, another fine contribution from you.
I once thought about actually MEASURING shoot-trough and align dead-time accordingly through a control loop with asymmetric timing. I.e. increase dead-time fast an decrease it slowly.
Regards
Charles
I still haven't received a reply from IR to my data sheet questions, but here is the zipped first-cut model of the IRS20954 driver IC.
These are LTspice-only files consisting of the hierarchical symbol, schematic and top level test schematic.
Regards -- analogspiceman
These are LTspice-only files consisting of the hierarchical symbol, schematic and top level test schematic.
Regards -- analogspiceman
These are LTspice-only files consisting of the hierarchical symbol, schematic and top level test schematic.
Regards -- analogspiceman
Thank You very much!
I still not get the time for a closer look to the specs and You present a model - great!
Regards
Heinz!
Regards -- analogspiceman
Thank You very much!
I still not get the time for a closer look to the specs and You present a model - great!
Regards
Heinz!
Okay, attached is a self oscillating style, class d example design showing the IRS20954 model in action. It is set up with a slightly low-ish operating frequency to speed run time. It goes through a soft start cycle, then idles a bit, then reproduces an increasing amplitude sine wave that eventually trips the current limit.
The .asc (LTspice schematic) extension is not an allowed file type for attachments posted to this forum, so the extension has been changed to ".txt" (you'll have to change it back after downloading). Be sure to put this new file (Class-D1.asc) in the same folder with the model files from the prior zip file.
Regards -- analogspiceman
PS: please report any model bugs that crop up, thx.
The .asc (LTspice schematic) extension is not an allowed file type for attachments posted to this forum, so the extension has been changed to ".txt" (you'll have to change it back after downloading). Be sure to put this new file (Class-D1.asc) in the same folder with the model files from the prior zip file.
Regards -- analogspiceman
PS: please report any model bugs that crop up, thx.
Csh is the OC is it?
I had no problems with it at all it ran just fine and did as expected...... awesome!
It seems to switch low again at about 96.6ms and then unless I miss my guess here freewheel current trips the overcurrent again?
I had no problems with it at all it ran just fine and did as expected...... awesome!
It seems to switch low again at about 96.6ms and then unless I miss my guess here freewheel current trips the overcurrent again?
classd4sure said:
Yes, it trips, resets, waits and trips again on the next input voltage peak - just look at the ramping voltage on the timing capacitor (C2) on the CSD pin.
For overcurrent protection, the IC somewhat crudely senses the on-voltage across each MOSFET. MOSFET on-resistance is a strong function of temperature (it goes up), so, so is overcurrent trip level (which, therefore, goes down). Trip currents (really voltages) for the two MOSFETs are set independently and normally would be designed, as much as possible, to be at the same setting. Obviously, the point of this IC's circuitry is to protect against gross load shorts on the amplifier output rather than provide laboratory grade current limiting. This method probably also offers quite a bit of protection against thermal overloads due to insufficient heat sinking. By the way, that reminds me - one caveat about amplifier simulations - LTspice MOSFET models do not provide dynamic thermal modulation of on-resistance. There are some complicated sub-circuit type MOSFET models that do, but they generally run so slowly as to be next to useless. Hmmm...
I'm surprised that no one has yet commented on the deadtime setting for this circuit. It's too short! Those few tens of nanoseconds do matter. Just look at the spikes in the MOSFET drain current, swap the values of R5 and R6 (adds 30ns to deadtime), then rerun and look again - no more spikes.
Regards -- analogspiceman
Hi,
I noticed the cross conduction when I looked at the gate waveforms last night. It wasnt' worth mentioning at all as it was obvious at the time this was a proof of concept sim for your gate driver model, and that worked flawlessly from what I saw. Commenting on the rest of it would only have been arrogant, and you know what you're doing.
I guess one option is always to shut down the amp entirely upon overcurrent, or enforce a longer delay before it retriggers, this could allow at least a general inspection for shorts and also allow more time to cool things down. Depends how bullet proof this ends up being.
I noticed a few mosfet models as you mentioned from fairchild, hardly worth the effort required to try them at this point.
It would be nice if you got a reply to your querries in order to perfect the model, but they possibly don't want to offer that kind of "support", and anyway, it's still just spice, maybe this is just perfect enough.
Thanks for doing it for us.
I noticed the cross conduction when I looked at the gate waveforms last night. It wasnt' worth mentioning at all as it was obvious at the time this was a proof of concept sim for your gate driver model, and that worked flawlessly from what I saw. Commenting on the rest of it would only have been arrogant, and you know what you're doing.
I guess one option is always to shut down the amp entirely upon overcurrent, or enforce a longer delay before it retriggers, this could allow at least a general inspection for shorts and also allow more time to cool things down. Depends how bullet proof this ends up being.
I noticed a few mosfet models as you mentioned from fairchild, hardly worth the effort required to try them at this point.
It would be nice if you got a reply to your querries in order to perfect the model, but they possibly don't want to offer that kind of "support", and anyway, it's still just spice, maybe this is just perfect enough.
Thanks for doing it for us.
I'm surprised that no one has yet commented on the deadtime setting for this circuit. It's too short! Those few tens of nanoseconds do matter. Just look at the spikes in the MOSFET drain current, swap the values of R5 and R6 (adds 30ns to deadtime), then rerun and look again - no more spikes.
Regards -- analogspiceman
analogspiceman,
thank You for the example, so far I see the model works fine!
If one reduce the Gate-Rs to 2E the current spikes seems
acceptable with short deadtime also the distorsion is quite low. But with 45ns it don´t looks good.
For test I used your older example.
Regards
Heinz!
Regards -- analogspiceman
analogspiceman,
thank You for the example, so far I see the model works fine!
If one reduce the Gate-Rs to 2E the current spikes seems
acceptable with short deadtime also the distorsion is quite low. But with 45ns it don´t looks good.
For test I used your older example.
Regards
Heinz!
....received the samples within 4 days!!! I love the modern world.
I am starting to play around with a halfbridge set up like the attached schematic. I disabled the high side over current protection, because my final amp will have a full bridge, means two over current protections in the lower legs will give full protection.
Don't wonder about the BYT86 for the boot strap, I just had it on hand...
In first step I selected the max dead time and set the OCSET to a small value (74mV).
Well... I thought this would be OK to start playing around and adjusting the gate drive (kept simple for first step, asymetric ON/OFF speed next..).
But for some reason the IC does not generate any output signal at all, even when driving the input signal into heavy clamping.
In general all signals/voltages are looking OK for me, except the gate drive signals which are constantly low. Consequently the halfbridge output is drifting with high impedance. The voltages/operating points in the schematic are taken with +/-16V rails. I guess, I am a victim of some shut down mechanism, which I am not aware off... RTFM once more...
Hints are welcome.
I am starting to play around with a halfbridge set up like the attached schematic. I disabled the high side over current protection, because my final amp will have a full bridge, means two over current protections in the lower legs will give full protection.
Don't wonder about the BYT86 for the boot strap, I just had it on hand...
In first step I selected the max dead time and set the OCSET to a small value (74mV).
Well... I thought this would be OK to start playing around and adjusting the gate drive (kept simple for first step, asymetric ON/OFF speed next..).
But for some reason the IC does not generate any output signal at all, even when driving the input signal into heavy clamping.
In general all signals/voltages are looking OK for me, except the gate drive signals which are constantly low. Consequently the halfbridge output is drifting with high impedance. The voltages/operating points in the schematic are taken with +/-16V rails. I guess, I am a victim of some shut down mechanism, which I am not aware off... RTFM once more...
Hints are welcome.
...the data sheet pushed me to change the voltage divider for OCSET.
IR proposes the range between 0.5V .... 5V.
My new divider is 8k2 and 1k2. Nope. This was not the reason.
Now I have 653mV at the OCSET pin, but still nothing is moving.
IR proposes the range between 0.5V .... 5V.
My new divider is 8k2 and 1k2. Nope. This was not the reason.
Now I have 653mV at the OCSET pin, but still nothing is moving.
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