The 20V rails are still ok when the amp goes to 6V?
/just read the problem seems to be solved…
I had a problem with LM317/337 as supply for input stage and put 10 ohms on the output to isolate from the load.
Can you upload the MC file ?
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I cranked it up with a variac, but as I remember when the PSU reached the 6V or so there was a huge current draw, so I then stopped cranking up.
The MC file is the new one, and not as complete as the CiKad file.
Hi,
Is your main heat-sink grounded?
I suppose you are not using a variac anymore, right?
Good luck.
M.
Is your main heat-sink grounded?
I suppose you are not using a variac anymore, right?
Good luck.
M.
For me the Simulation not works correctly, I think some models missing...
I did a few changes and played around a bit
Is it normal that the output Transistors turn off completely when applying a sine?
I did a few changes and played around a bit
Is it normal that the output Transistors turn off completely when applying a sine?
In post # 62
There is absolutely no need to use a 50 watt power transistor for second gain stage Q6.
gain is poor for small signal Ft very low
Would take a considerably amount of current for Q2 and Q3 to drive it.
and to maintain balance.
Without going into extreme detail
R6 is likely way to high to be able to drive Q6
Would expect the same issues as last time.
Massive DC offset around 35 to 65 mv
and to get any balance, likely have to crank up the current
of Q2 and Q3. way beyond what the need to be
and just encourage even more instability
and far to much current in the first gain stage.
with no degen.
= oscillator , DC offset, and big start up thump
C6 also pointless , using more modern matched output devices.
only necessary for ancient slow mismatched power transistors or drivers
where usually the NPN or PNP would be faster and one side would need to be slowed down
so it doesn't oscillate at high frequency.
Hence why CFP never very common. to much cross conduction
and in early days with slower mismatched power transistors
to make it even work you would use C6. and the overall
compensation needed for C5 would be in the stratosphere
around 220 to 300p.
far as the oscillation issue of the first design
would likely be what solves it.
cdom would have to be well over 100p.
be around 220 to 300p
and remove C6
if your not going to use a current mirror
for Q2 and Q3. and are going to keep current levels
reasonable. you would need to severely reduce the load they drive.
and just use the same TO92 equivalent for Q6
There is absolutely no need to use a 50 watt power transistor for second gain stage Q6.
gain is poor for small signal Ft very low
Would take a considerably amount of current for Q2 and Q3 to drive it.
and to maintain balance.
Without going into extreme detail
R6 is likely way to high to be able to drive Q6
Would expect the same issues as last time.
Massive DC offset around 35 to 65 mv
and to get any balance, likely have to crank up the current
of Q2 and Q3. way beyond what the need to be
and just encourage even more instability
and far to much current in the first gain stage.
with no degen.
= oscillator , DC offset, and big start up thump
C6 also pointless , using more modern matched output devices.
only necessary for ancient slow mismatched power transistors or drivers
where usually the NPN or PNP would be faster and one side would need to be slowed down
so it doesn't oscillate at high frequency.
Hence why CFP never very common. to much cross conduction
and in early days with slower mismatched power transistors
to make it even work you would use C6. and the overall
compensation needed for C5 would be in the stratosphere
around 220 to 300p.
far as the oscillation issue of the first design
would likely be what solves it.
cdom would have to be well over 100p.
be around 220 to 300p
and remove C6
if your not going to use a current mirror
for Q2 and Q3. and are going to keep current levels
reasonable. you would need to severely reduce the load they drive.
and just use the same TO92 equivalent for Q6
I saw that in practive using a small resistor ( 4.7 ohm ' ish ) in the bases of the output transistors might solve the oscillations in a CFP.
It is possible, but not as simple to implement with this topology.
And for the simplicity/parts count vs performance not needed.
It is why it is very much a favor with many.
compared to topology in post #67 similar to P3A and many others.
Distortion wont be much better than .05 to .01 %
it takes a more generous parts count like mirror , beta enhancement etc etc
to bring it to distortion ratings closer to .008 to .001 %
Topology in post #69 uses same low parts count
but already achieves .008 to .005% distortion
without any additional upgrades.
More useful when using multiple output transistors for higher power.
much more common with EF stages.
As far as a single pair of devices with CFP
No , it can actually cause more oscillation if too high of value.
and once the value is low enough. it does not significantly reduce
high frequency ringing or straight high frequency oscillation of a CFP.
the significant contribution to stability in post #67
in real world application. is the usual methods.
C9, C10, C11, C12 would be placed as close as possibly
to output power transistors. pretty normal.
as far as the bain of a CFP high frequency ringing/oscillation.
and what actually stabilizes it, most stabilize the thing with absurd amounts
of cdom capacitor C6 in post #67.
Usually very high around 220p to even 300p.
The real key is to reduce load to T1,T2
should only take 2ma to balance the amplifier.
If extremely low values below 680 ohms is needed
for R4. and you start cranking up current to 2.5ma to 3ma
To get the tail to balance and output DC offset low.
Then T6 is much too difficult to drive and has poor gain.
R4 should be high around 820 to even 1k
meaning second gain stage is easy to drive.
I could even raise it to 3.3K but that would require
a Darlington driver for T6 second gain stage.
often called beta enhancement.
Which significantly reduces the load on the first gain stage.
in fact to maintain balance overall current for the CCS would not
even be 2ma, could be even lower @ 1ma
As you see in post #67 R4 is 820
and only 2ma of current is needed to balance the differential.
DC offset on the amplifier output is very low around 2 mV
P3A and many others usually dont achieve that balance and DC
offset on output is usually very high around 18 to even 35 mV.
R4 could be 560 to 680 and usual absurd amounts of current
of around 2.5ma to 3ma are used. and overall DC offset
is still poor 15 to 30mV
Main contribution to finally cure high frequency oscillation
is Degen resistors R20 , R21 specified as E196 series resistors
with .1 % tolerance.
As you see C6 cdom is not a ridiculous 220p to 300p
it is only 47p and all that is needed.
Because R20, R21 degen resistors significantly cures the high frequency
issues so well.
Another contributor is C7 and and C3 placed around T5
VBE multiplier. in all simplicity 10n will catch high frequency ringing
that the output stage barfs into it. 10u will
stabilize the VBE voltage ref.
this in general will help stabilize any basic CFP or EF output stage.
and often 10n to 100n is only needed since the main contribution
is reducing high frequency ringing.
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With regard to the diagram in post 64, my observations:
1. No need for two series input resistors. I usually put any RF filter resistor connecting to the base of the input transistor (R3) and the input capacitor, with the filter capacitor connected from base to ground across the bias resistor (R2, here). This keeps the nominal base impedances on the two sides the same. so this just means that the circuit mentioned, R3 is not required. This also keeps the base of the input transistor at a low impedance which helps with stability.
2. R25 is redundant, as it serves little purpose unless it is essential to match the two collector voltages, which in my experience is not essential when they are tens of volts, or thereabouts, or, if it is preferable, use a cascode on the input, which here is more complicated and not essential.
3. The current sources I use tend to be passive types, which although rarely, I have seen feedback types contributing to instability (HF oscillation). One of the best I've seen is Bailey's circuit which uses a 10V Zener to stabilise the voltage across the CCS transistor; a 5.6V Zener to provide a base reference voltage, 2.2k resistors for the CCS transistor emitter (giving just under 2mA at 5V) and 2.2k feeding the 5.6V Zener from the centre (ground) rail. The 10V zener has to be supplied with about 5mA, so a suitable series resistor is in the region of 1-2k depending on the power supply voltage. This has to be 1 or 2W (also depending on the dissipation) but it is a very stable CCS.
For the VAS stage, a couple of diodes as shown in an earlier post is generally acceptable, I find. If you need better stability, or a better constant current, using higher rail voltages and higher bias voltages (like a zener) would be an improvement, but I've used the diode pair in several amplifiers successfully.
4. A miller capacitor compensation is stable, and does not need R24. C6 may not be needed for asymmetry but has an additional effect on the overall gain roll-off that adds to the Miller effect. If you are going to degenerate the input stage, then you are close to implementing Self's Blameless as you may need an additional pre-VAS transistor to make up the lost gain. If you are going to degenerate the VAS stage, then there may be no need for a Miller capacitor, so the circuit as posted does not optimise either approach. One argument for a series resistor in the VAS emitter would be to provide some current limiting, possibly combined with a couple of diodes as though it were a current source (connected across the bias resistor), and for that purpose would typically be just under half the resistance of the resistor used in the CCS. But that would make it 47 ohms, even higher than the 27 shown, so would probably impact THD adversely, although stability might be a lot better. You could however route the bias resistor to the emitter (leaving the upper diode connected to the rail) and that would eliminate the gain reduction, in the main.
5. The circuit is likely to show slew rate limiting as is well known for a Miller capacitor stabilised circuit without degen resistors - or even with degen resistors if the current drive is not high enough. Hence my comments about it may need further optimisation.
6. Oscillation in a CFP output stage is more likely with high speed transistors. That is one reason to keep C6. However, as simulated in my approximation (input stage &CCS BC546B's, drivers BD139-140, VAS BD140, CCS BD139, OPT's MJL1802/3281 crossover distortion at 20kHz was present and due to instability in the OPS. That can be countered with 10 ohm resistors in series with the driver transistor emitters. That helps to suppress shoot-through current, but a "feature" of the CFP stage is that the drivers do have to conduct a sudden "jump" in current when the off device turns on, which always simulated as being higher than the standard EF circuit. Distortion as sim'd reduced from 0.3% to 0.06% at 20kHz with the emitter resistors. This will place a burden on the input stage and feedback, so there will be a mechanism for higher frequency distortion present which can only be offset with higher OLG e.g. Blameless configuration but with CFP output.
1. No need for two series input resistors. I usually put any RF filter resistor connecting to the base of the input transistor (R3) and the input capacitor, with the filter capacitor connected from base to ground across the bias resistor (R2, here). This keeps the nominal base impedances on the two sides the same. so this just means that the circuit mentioned, R3 is not required. This also keeps the base of the input transistor at a low impedance which helps with stability.
2. R25 is redundant, as it serves little purpose unless it is essential to match the two collector voltages, which in my experience is not essential when they are tens of volts, or thereabouts, or, if it is preferable, use a cascode on the input, which here is more complicated and not essential.
3. The current sources I use tend to be passive types, which although rarely, I have seen feedback types contributing to instability (HF oscillation). One of the best I've seen is Bailey's circuit which uses a 10V Zener to stabilise the voltage across the CCS transistor; a 5.6V Zener to provide a base reference voltage, 2.2k resistors for the CCS transistor emitter (giving just under 2mA at 5V) and 2.2k feeding the 5.6V Zener from the centre (ground) rail. The 10V zener has to be supplied with about 5mA, so a suitable series resistor is in the region of 1-2k depending on the power supply voltage. This has to be 1 or 2W (also depending on the dissipation) but it is a very stable CCS.
For the VAS stage, a couple of diodes as shown in an earlier post is generally acceptable, I find. If you need better stability, or a better constant current, using higher rail voltages and higher bias voltages (like a zener) would be an improvement, but I've used the diode pair in several amplifiers successfully.
4. A miller capacitor compensation is stable, and does not need R24. C6 may not be needed for asymmetry but has an additional effect on the overall gain roll-off that adds to the Miller effect. If you are going to degenerate the input stage, then you are close to implementing Self's Blameless as you may need an additional pre-VAS transistor to make up the lost gain. If you are going to degenerate the VAS stage, then there may be no need for a Miller capacitor, so the circuit as posted does not optimise either approach. One argument for a series resistor in the VAS emitter would be to provide some current limiting, possibly combined with a couple of diodes as though it were a current source (connected across the bias resistor), and for that purpose would typically be just under half the resistance of the resistor used in the CCS. But that would make it 47 ohms, even higher than the 27 shown, so would probably impact THD adversely, although stability might be a lot better. You could however route the bias resistor to the emitter (leaving the upper diode connected to the rail) and that would eliminate the gain reduction, in the main.
5. The circuit is likely to show slew rate limiting as is well known for a Miller capacitor stabilised circuit without degen resistors - or even with degen resistors if the current drive is not high enough. Hence my comments about it may need further optimisation.
6. Oscillation in a CFP output stage is more likely with high speed transistors. That is one reason to keep C6. However, as simulated in my approximation (input stage &CCS BC546B's, drivers BD139-140, VAS BD140, CCS BD139, OPT's MJL1802/3281 crossover distortion at 20kHz was present and due to instability in the OPS. That can be countered with 10 ohm resistors in series with the driver transistor emitters. That helps to suppress shoot-through current, but a "feature" of the CFP stage is that the drivers do have to conduct a sudden "jump" in current when the off device turns on, which always simulated as being higher than the standard EF circuit. Distortion as sim'd reduced from 0.3% to 0.06% at 20kHz with the emitter resistors. This will place a burden on the input stage and feedback, so there will be a mechanism for higher frequency distortion present which can only be offset with higher OLG e.g. Blameless configuration but with CFP output.
Bernhard, MaxLorenz, WhiteDragon, xXBrunoXx and john_ellis. Thank you for your interest in this thread, very informative posts.
On this background I will re consider my hole project, and study in more depth what you are saying, and study some literature on this topic. I have a pdf cpy of Bob Cordell's "Designing Audio Power Amps", that might be a starting point.
So it will probably take a little before I am back again with news on the progress.
On this background I will re consider my hole project, and study in more depth what you are saying, and study some literature on this topic. I have a pdf cpy of Bob Cordell's "Designing Audio Power Amps", that might be a starting point.
So it will probably take a little before I am back again with news on the progress.
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Happy and Prosperous New Year to you all!
On the contrary thanks to you for such an enlightening thread. I recently explored a couple of comparable amps like Ampslab C200 Siklai (which I modded as a "LTMD" amp 🤓) but now I understand why it did not work when powered from a POWERREGed regulated supply but worked flawlessly from a normal linear supply...and other tips...
Best wishes
M.
On the contrary thanks to you for such an enlightening thread. I recently explored a couple of comparable amps like Ampslab C200 Siklai (which I modded as a "LTMD" amp 🤓) but now I understand why it did not work when powered from a POWERREGed regulated supply but worked flawlessly from a normal linear supply...and other tips...
Best wishes
M.
Yes Max, happy new year to all.
I have now studied Bob Cordells Designing Audio Power Amplifiers Fist edition.
I have studied especially chapter 3 Power Amplifier Design Evolution. I have chosen Figure 3.10 on page 65 as my starting point. This thread is about "My first CFP power amp", so I have changed BC's emitter follower output in fig 3.10 to an CFP output stage. In the simulation it seems to be ok. My first idea vas the CFP, so I will stick to that. I have attached a jpg with the schematic.
Next is to draw the schematic in KiCad and implement the principle from my last try, where I will keep the power rails as close to each other and avoid as many loop like tracks as possible. I am looking forward to do just that.
And as usual you are all welcome to comment what I am doing.
Again Happy New Year to all.
Henrik
I have now studied Bob Cordells Designing Audio Power Amplifiers Fist edition.
I have studied especially chapter 3 Power Amplifier Design Evolution. I have chosen Figure 3.10 on page 65 as my starting point. This thread is about "My first CFP power amp", so I have changed BC's emitter follower output in fig 3.10 to an CFP output stage. In the simulation it seems to be ok. My first idea vas the CFP, so I will stick to that. I have attached a jpg with the schematic.
Next is to draw the schematic in KiCad and implement the principle from my last try, where I will keep the power rails as close to each other and avoid as many loop like tracks as possible. I am looking forward to do just that.
And as usual you are all welcome to comment what I am doing.
Again Happy New Year to all.
Henrik
Hi again. I have a question. The bias splitter (Q5) should normally be thermal connected to the first CFP transistor (Q8), but since we have the buffer in between (Q16 & Q17) should Q5 still be connected to Q8 or should it connect to Q16?
My analysis is, that Q16 have more constant current flow and hence more even temperature regardless of the signal, where as the current flow varies a lot with the signal in Q8, and therefore the thermal connection between Q5 to Q8 would prevent thermal runaway. Is this right?
My analysis is, that Q16 have more constant current flow and hence more even temperature regardless of the signal, where as the current flow varies a lot with the signal in Q8, and therefore the thermal connection between Q5 to Q8 would prevent thermal runaway. Is this right?
Ideally, one would want two series Vbe multipliers: one to track Q16/17 and another to track Q8/Q9. However, since the former run at nearly constant current and the latter can have big enough heat sinks to minimize temperature rise, thermal tracking may not be needed at all.
Ed
Ed