You can use 1ma if you change resistor R1 to 1.5K Ohm. You have to bias the base of Q1 with 1ma or 0.7V/700 Ohm. Therefore, if Q5 has 1ma and Q6 must also have 1ma then the current of Q8 must be 2ma.Hi James
I can see that many LTP's is running at only 1mA, but I am open to experiments, so I will try 2mA as well.
But is there a specific reason for you to suggest the 2mA?
Thanks.
Henrik
James
Hi James, elementary, and thanks for your answer.You can use 1ma if you change resistor R1 to 1.5K Ohm. You have to bias the base of Q1 with 1ma or 0.7V/700 Ohm. Therefore, if Q5 has 1ma and Q6 must also have 1ma then the current of Q8 must be 2ma.
James
To day I have made some changes, I added an LM7805 to feed the current mirror/sink.
I have tested the amp, and as anticipated by you guys (thank you), the heavy current draw when turned on with load disappeared.
So Now I can measure the amp while running.
When I raised the output bias current I saw a 2 MHz oscillation with a Vp of around 430mV when the bias was >31mA.
I have moved wires around without any improvement or change at all.
The AC current draw is only 147 mA, but I want to get rid of it one way or the other.
So if any of you have a hint, you are welcome.
To morrow I will make the CSS with diodes and se how i works.
The simulation of the LTP is quite misleading regarding dc operating points, that goes for both Simetrix and Micro-Cap.
So I will perform some measurements on both channels, hopefully to morrow.
I take this as a learning process to get this am up and running.
Henrik
I have tested the amp, and as anticipated by you guys (thank you), the heavy current draw when turned on with load disappeared.
So Now I can measure the amp while running.
When I raised the output bias current I saw a 2 MHz oscillation with a Vp of around 430mV when the bias was >31mA.
I have moved wires around without any improvement or change at all.
The AC current draw is only 147 mA, but I want to get rid of it one way or the other.
So if any of you have a hint, you are welcome.
To morrow I will make the CSS with diodes and se how i works.
The simulation of the LTP is quite misleading regarding dc operating points, that goes for both Simetrix and Micro-Cap.
So I will perform some measurements on both channels, hopefully to morrow.
I take this as a learning process to get this am up and running.
Henrik
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There are at least 2 possible sources of oscillation. Firstly, you should temporarily make C5 100 times larger to see if the loop stabilizes since this capacitor kills the loop gain and it could be undersized in the application. Resizing C5 may stop the oscillation but if it doesn't then there may be a local oscillation in the output stage. There could be a local oscillation caused by C7. The Q9 and Q12 configuration may cause local oscillation if Q9 is much slower than Q12 which is usually true because NPNs are inherently 3 times faster than PNPs. The addition of C7 may contribute to the local oscillation as it tends to slow Q9 even more. C7 may be more useful if it was used to slow Q12 by placing it across Q12's drain to gate. You will have to try some different values of C7 or change its connection to determine if the oscillation is a local output stage oscillation. My statements are educated guesses at this point and there may be other sources of oscillation that I have not predicted.
James
James
I'll speculate about your latchup:Hi all!
It has ben many years since my last post here, I guess some 20 years, I am now retired an have some more time to my Hobby.
I am working on this CFP, which causes me som troubles.
I would be wery thankful if any of you could give me a hint to solve my little problem.
I have attached files to give you an idea of my project.
Micro-Cap schematic:View attachment 1115526
Kicad schematic:View attachment 1115527
KiCad pcbView attachment 1115528
KiCad 3DView attachment 1115529
Pcb under testView attachment 1115530
Test setup:View attachment 1115533
Here is the problem:
1. When I power up the amp without speaker connected all is fine and dc off set at the output terminals is 70mV. After powering up I can connect the speaker and hear some music.
2. Powering up with the speaker connetcted causes the amp to draw a lot of current, and I have 6V on the terminals.
3. Powering up with a cap in series with the speaker, all is fine and I have music in the speaker.
4. Powering up with an 120 ohm resistor in series with the speaker also does the trick, with les music volume of cause.
I really would appreciate som help, please!
Henrik
You have no current mirror at R1, and current source at Q10. that means at power up, Q10 comes on before the IPS gets Q1 going. This creates a huge negative voltage startup thump, which exceeds the Vbe limit of Q6. Note the reference designators do not match so I will use the Kicad.
I suggest
1. Clamping diodes on C7 so that the feedback divider also reduces any DC feedback.
2. A current mirror so that Q1 starts sooner and does not wait for the IPS to reach full current.
3. And/or you could slow down the startup of current source Q10 with a large cap on the base of Q10.
But why a load makes any difference, I dunno. Maybe there is a grounding problem.
In a few cases I have been able to localize the oscillation by touching different points on the PCB while watching the scope. It's a very high frequency, so I'm thinking a local loop, a global loop usually oscillates on a lower frequency.
Many of the schematics don't seem to show 0.1uF supply bypass caps (as seen in post #37).
Make sure they are there in your breadboard. And check the rails for presence of the oscillation--- should be very small, i.e. suppressed, small re 430mV shown in #43. Their leads should be short, near the output transistors.
Make sure they are there in your breadboard. And check the rails for presence of the oscillation--- should be very small, i.e. suppressed, small re 430mV shown in #43. Their leads should be short, near the output transistors.
I had one channel up and running with around 150mV 2MHz oscillation, and then something went wrong and the amp had a asymmetrical current draw. so back to square one. Then I populated a new pcb, and unfortunately I got the same asymmetrical current draw. So I have decided to populate a new pcb in stages covering:
1: LTP
2: LTP + VAS CCS with load resistor
3: LTP + VAS CCS with upper BJT
4: LTP + VAS CCS with upper BJT and bias spread.
5: LTP + VAS + Drivers
6: Full amp
I have attached a pdf with the stages.
I will then measure and analyse the circuit in these stages to hopefully find the error(s).
I have changed the CCS from current mirrors to a conventional CCS made up of two transistors (see the pdf).
For now I have mad the LTP stage, witch acts as one could expect, so to day I will continue the work in progress.
Hopefully at the end of the day I will have an functionally amp with no or little oscillation.
I have omitted the 22pf feedback cap and removed the zobel network from the position above the output BJT's on the pcb so I can move it around to find the best position.
Henrik
1: LTP
2: LTP + VAS CCS with load resistor
3: LTP + VAS CCS with upper BJT
4: LTP + VAS CCS with upper BJT and bias spread.
5: LTP + VAS + Drivers
6: Full amp
I have attached a pdf with the stages.
I will then measure and analyse the circuit in these stages to hopefully find the error(s).
I have changed the CCS from current mirrors to a conventional CCS made up of two transistors (see the pdf).
For now I have mad the LTP stage, witch acts as one could expect, so to day I will continue the work in progress.
Hopefully at the end of the day I will have an functionally amp with no or little oscillation.
I have omitted the 22pf feedback cap and removed the zobel network from the position above the output BJT's on the pcb so I can move it around to find the best position.
Henrik
Attachments
Hi James, thanks for your constructive procedures and explanations, I will definitely use them when I shall track down the oscillations.There are at least 2 possible sources of oscillation. Firstly, you should temporarily make C5 100 times larger to see if the loop stabilizes since this capacitor kills the loop gain and it could be undersized in the application. Resizing C5 may stop the oscillation but if it doesn't then there may be a local oscillation in the output stage. There could be a local oscillation caused by C7. The Q9 and Q12 configuration may cause local oscillation if Q9 is much slower than Q12 which is usually true because NPNs are inherently 3 times faster than PNPs. The addition of C7 may contribute to the local oscillation as it tends to slow Q9 even more. C7 may be more useful if it was used to slow Q12 by placing it across Q12's drain to gate. You will have to try some different values of C7 or change its connection to determine if the oscillation is a local output stage oscillation. My statements are educated guesses at this point and there may be other sources of oscillation that I have not predicted.
James
Hi SteveuI'll speculate about your latchup:
You have no current mirror at R1, and current source at Q10. that means at power up, Q10 comes on before the IPS gets Q1 going. This creates a huge negative voltage startup thump, which exceeds the Vbe limit of Q6. Note the reference designators do not match so I will use the Kicad.
I suggest
1. Clamping diodes on C7 so that the feedback divider also reduces any DC feedback.
2. A current mirror so that Q1 starts sooner and does not wait for the IPS to reach full current.
3. And/or you could slow down the startup of current source Q10 with a large cap on the base of Q10.
But why a load makes any difference, I dunno. Maybe there is a grounding problem.
Changing the CCS from PSU depended to un depended as Rory Christ suggested did the trick with regard to the load problem and the heavy current draw.
But why it cured the load problem I dont know, but it did, but there could be a grounding problem.
If the latchup is still there I will try your recommendations, so many thanks for sharing your knowledge.
Henrik
I will bare this method in mind when tracking down the oscillation.In a few cases I have been able to localize the oscillation by touching different points on the PCB while watching the scope. It's a very high frequency, so I'm thinking a local loop, a global loop usually oscillates on a lower frequency.
Thanks for your comment.
Henrik
Hi BSSTMany of the schematics don't seem to show 0.1uF supply bypass caps (as seen in post #37).
Make sure they are there in your breadboard. And check the rails for presence of the oscillation--- should be very small, i.e. suppressed, small re 430mV shown in #43. Their leads should be short, near the output transistors.
In my KiCad schematics they are there and on the pcb as well close to the electrolytic caps.
I have not checked for oscillation at the PSU input at the PCB, but I will.
The PSU leads are not shot in post #43, but in my new setup they are twisted, I hope this will help, but I will try short PSU leads as well.
Thanks for your advice.
Henrik
Hi OldDiy
Very educational, thanks.
Hi all
I have decided to update the schematic and make some new PCB design.
I have read in some thread here on diyAudio (I tried to find it without any luck), that you should try to keep + and - rails as close as possible to each other, and not make connections like daisy-chains.
I guess that you then have to make the rails as a bus, and from there connect to every single component, and likewise with the GND connections.
That I have never done, bout it sounds very reasonable to do so. But I had some doubt to how it should be done, but as the work progressed it seemed to be doable. So here is the new KiCad schematic and the KiCad PCB layout as a work in progress.
Comments are very welcome.
Henrik
I have decided to update the schematic and make some new PCB design.
I have read in some thread here on diyAudio (I tried to find it without any luck), that you should try to keep + and - rails as close as possible to each other, and not make connections like daisy-chains.
I guess that you then have to make the rails as a bus, and from there connect to every single component, and likewise with the GND connections.
That I have never done, bout it sounds very reasonable to do so. But I had some doubt to how it should be done, but as the work progressed it seemed to be doable. So here is the new KiCad schematic and the KiCad PCB layout as a work in progress.
Comments are very welcome.
Henrik
I can see that when I scaled the vector based drawings, the tracks was not scale able, so they are some what thinner than the original ones.
This is corrected here and the size of the board is 100mm x 58mm.
This is corrected here and the size of the board is 100mm x 58mm.
You have a clean ground and a dirty ground separated by R21. The ground connection of C1, C2, C12 and C13 should be to the dirty ground, not the clean ground. Pay attention to the order in which grounds return to the main ground terminal. Dirty grounds such as power capacitors should connect to the ground bus through a separate trace from the sensitive audio grounds. Some even go so far as to run a separate ground wire from the clean ground back to the main power supply.Hi all
I have decided to update the schematic and make some new PCB design.
I have read in some thread here on diyAudio (I tried to find it without any luck), that you should try to keep + and - rails as close as possible to each other, and not make connections like daisy-chains.
I guess that you then have to make the rails as a bus, and from there connect to every single component, and likewise with the GND connections.
That I have never done, bout it sounds very reasonable to do so. But I had some doubt to how it should be done, but as the work progressed it seemed to be doable. So here is the new KiCad schematic and the KiCad PCB layout as a work in progress.
View attachment 1121724
View attachment 1121725
View attachment 1121726
View attachment 1121727
View attachment 1121728
Comments are very welcome.
Henrik
What is the copper plane on top of the output transistors for? it looks like it's floating, which makes it an antenna for noise.
When doing a layout it's best to keep in mind the loop area of traces. Try to keep source and return traces as close together as possible. + and - rails should run parallel if possible. Feedback and ground traces too This cuts down on the radiated noise from the traces (and possibly sources of oscillation). Ground and power traces should be large.
You have no Zobel network or output inductor. These don't need to be on the actual amplifier board but should be added to the finished amplifier chassis to keep noise from the outside world out of your amplifier.
Hi jwilhelmYou have a clean ground and a dirty ground separated by R21. The ground connection of C1, C2, C12 and C13 should be to the dirty ground, not the clean ground. Pay attention to the order in which grounds return to the main ground terminal. Dirty grounds such as power capacitors should connect to the ground bus through a separate trace from the sensitive audio grounds. Some even go so far as to run a separate ground wire from the clean ground back to the main power supply.
Thank you for your answer, they are really useful to me.
I will change the location of C1, C2, C12 and C13.
I think I will run a separate ground wire from signal GND to PSU, that was my initial thought, but also to make the PCB that I can try other ways of grounding.
I will look deeper into your thoughts and hints to morrow, and come up with a new schematic.
Thank you
Henrik
I have attached a pdf with an updated schematic.
The copper plane is connected to Power GND via JP1 close to Power GND input terminal.
(1) +rail, GND and -rail side by side on the back copper layer.
(2) +rail and -rail at the back copper layer and then the GND bus at the front copper layer.
Scenario 1 have the advantage of facilitating other tracks to cross +rail, GND and -rail on the front copper layer without a jumper as would be necessary in scenario 2.
So for now I continue with 1.
Thanks jwilhelm
I will be back later with some updates, but it's Christmas, so I have to keep up that Christmas social life for a little while.
Henrik
The copper plane is there to shield I guess, I saw Rod Elliot doing it on his PCB, but he might have done it for other reasons.What is the copper plane on top of the output transistors for? it looks like it's floating, which makes it an antenna for noise.
The copper plane is connected to Power GND via JP1 close to Power GND input terminal.
I am redesigning my first draft (CFP_Power_amp_V2b) into the next CFP_Power_amp_V2c. I am minimising the loops once more.When doing a layout it's best to keep in mind the loop area of traces.
I have two scenarios:Try to keep source and return traces as close together as possible.
(1) +rail, GND and -rail side by side on the back copper layer.
(2) +rail and -rail at the back copper layer and then the GND bus at the front copper layer.
Scenario 1 have the advantage of facilitating other tracks to cross +rail, GND and -rail on the front copper layer without a jumper as would be necessary in scenario 2.
So for now I continue with 1.
I will keep the rails as parallel as possible, but just around the electrolytes it is not possible.+ and - rails should run parallel if possible. Feedback and ground traces too This cuts down on the radiated noise from the traces (and possibly sources of oscillation).
GND traces i will try to keep 3mm wide and the +/-rails 2mm wide except for the connection to the output transistors where they are 3mm.Ground and power traces should be large.
In my first version I had the zobel network on the PCB, they were mounted on top of the output transistors, which caused oscillation, so I removed them, which halved the oscillation. I will mount them somewhere inside the amp chassis.You have no Zobel network or output inductor. These don't need to be on the actual amplifier board but should be added to the finished amplifier chassis to keep noise from the outside world out of your amplifier.
Thanks jwilhelm
I will be back later with some updates, but it's Christmas, so I have to keep up that Christmas social life for a little while.
Henrik
Attachments
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