I don't really know what you and Toshiba did decades ago, but it is not a secret about FETs, that one can alter some parameters of a FET by changing it's geometry (e.g. channel width against length) in order to reach a certain gm.
At a given chip area/capacitance you can then at least adjust gm to a certain target value, while leaving the capacitances rather untouched.
This kind of "matching" would lead into two "complementary" devices, which are perhaps equal in two or three parameters, but the rest would vary even much more (think about Early effect, leakage currents etc. etc.).
The trick to select simply a higher voltage rated N-Device will probably lower the differences in the above described manner, but it will never ever solve the matching problem.
The best solution for the matching of complementary devices is not using them in a complementary way, so you needed decades to solve a problem with your Blowtorch, which actually never existed !
The best matching of complementary FETs was btw. probably reached with the power V-FETs (SITs) from Sony in the early seventies.
john curl said:
MOSFETs are my preferred output devices. No second break down, a lot faster and less high order crossover harmonics (7th!!!).
But listen John, I've learned a lot from from you, for example that JFETs are (slightly) less noisier than BJTs. But.. please.. don't provoke me with that Bybee BS (or burning in of wires). If you do so you, I really can't resist the temptation to poke fun at it.
Cheers,
Edmond.
JFETs
Indeed, far much lower. But my focus is directed towards power amps, rather than electrometers that are supposed to count electrons. 😉
Cheers,
Edmond.
dimitri said:
Indeed, far much lower. But my focus is directed towards power amps, rather than electrometers that are supposed to count electrons. 😉
Cheers,
Edmond.
input bias current
Hi Dimitri,
Using an AD797 (at the front-end for example) with a input bias offset of 100nA and giving 10kOmhs resistors at the inputs and a gain of say 30x, that will result in an offset of 30mV at the output. Is that a problem?
Cheers,
Edmond.
Hi Dimitri,
Using an AD797 (at the front-end for example) with a input bias offset of 100nA and giving 10kOmhs resistors at the inputs and a gain of say 30x, that will result in an offset of 30mV at the output. Is that a problem?
Cheers,
Edmond.
The offset will change with the input signal, as charging and discharging paths are different. Do you this additional signal?
john curl said:
Real men don't match FETs. Real men use feedback.
(This is also a joke. OK, that's the intend.... I think.)
Jan Didden
SY said:
Too esoteric. The majority carrier mobilities in the N vs P FETs cause several problems. The match of the "beta" parameter between, for instance, the 2SK170/2SJ74 is actually pretty good. That means the gm's at equivalent Id's are fairly well matched. The doping concentrations unfortunately give large differences in Cgs/Cgd as well as not very well matched output impedances. The P FET's remain free of excess gate current as a side benefit.
scott wurcer said:
That, but mostly the 2...3 factor in area. Matching P/N gm requires W/L 2...3 times larger. Hence, larger area, Cgs and Cgd. The lack of excess gate current in P devices follows the same electron/hole assymetry. Holes have lower diffusion coefficient, hence lower diffusion current in the gate region. BTW, "beta" is proportional to the majority carier mobility.
syn08 said:
The "beta" parameter can be leveraged with Z/L at the expense of the capacitances. If you line up the 2SK74/2SK170 datasheets the Yfs/Id curves sort of line up.
- Status
- Not open for further replies.