Jitter blocking

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#83
Nixie said:
So I don't misunderstand you, give a description of the operation. I understand if you cannot show the VHDL, but you can still give an overview.
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The systeme is totally synchronous with the DAc oscillator. It samples the incoming CS8416 I2S signal, select 1 data corresponding to a CS8416 SCK edge, stores it in the SRAM and the the data is output according the DAC SCK.
After a few hours the 0.2s FIFO can get full or empty but it never happens because the FIFO is reinitialised whenever the data is a long silence (track change ou disc change). Read and Write access to the SRAM are quick so I wrote the VHDL so that it never happens at the same time. There is a period of time reserved for reading and one for writting.
 
#85
Hi Dan,


Well the ASRC project hasn't gone much further as a standalone part. The DAC however is done and is being sampled now to customers. The basic idea is that it is a 8 channel DAC capable of 128dB DNR and 120dB THD+N in 8 channel mode. It can aslo be run in 2 channel mode with 132 dB DNR and 120dB THD+N. Now im going to work on an audio ADC which should be fun. Anyways, im not sure where the marketing group is in what they call the "rollout" but I do know there should be some news of the part being made public soon. If there is a particular project or product you have in mind for this DAC, let me know and ill see if I can get you some engineering samples if you like.


THanks

CLD
 
#87
Dear CLD,
I know of / I am involved in something particulary related, so I would like to ask for prelim. datasheet / notes / sample of the DAC of yours. Please contact me via: readswift [.. at .. ] gmail . com , thanks..!
 
#88
Hi CLD,

Is there any news about the ASRC project? We haven't heard from you in a while.

I have rigged up one of your ASRC demo boards to convert the SPDIF output of a media streamer and it sounds pretty good. (I'm using the demo board that you sent to Fast Eddy). I rigged it with a 24.576M Crystek oscillator (0.5pS jitter spec) and decoupled the 3.3V a little bit.

I would be interested in a few IC samples if you have any left.

Please contact me at rossl -at- columbus.rr.com
 
#91
#92
Hi Jan,
Good to see your posts around here!

I am interested in jitter reduction on a SPDIF input for my system. I am looking at the usual CS8416 interface chip with the TORX142 optical module but I was concerned about jitter.

Looks to me like both the CS8416 and the LMK03000 are both just PLLs and as such will always jitter - you only get to choose the jitter noise spectrum depending on the loop filter parameters if I remember correctly. Do you have ideas why the National PLL is better than the Cirrus PLL?
 
#93
Actually, looking at the jitter attenuation specs:

the CS8416 rolls off at about 20dB/decade above 12KHz with a 2dB peak in the passband.

the LMK03000 rolls off at about 40dB/decade above 6KHz with a butterworth response.

Does this make a difference? I've no idea. Is it better? Certainly seems so but are there any disadvantages like slow lock time?

Well you've peaked my interest enough to look at the price😀

$13 is OK, but the LLP package isn't very DIY friendly.
 
#95
Dustin

I find it difficult to understand how your ASRC can be ready for production 18 months ago and now it's gone no further. Now you have a DAC which seems to be going along teh same route.

Isn't it time you brought home the bacon?

Gopher
 
#96
Iain McNeill said:
Actually, looking at the jitter attenuation specs:

the CS8416 rolls off at about 20dB/decade above 12KHz with a 2dB peak in the passband.

the LMK03000 rolls off at about 40dB/decade above 6KHz with a butterworth response.

Does this make a difference? I've no idea. Is it better? Certainly seems so but are there any disadvantages like slow lock time?

Well you've peaked my interest enough to look at the price😀

$13 is OK, but the LLP package isn't very DIY friendly.
Click to expand...


Neither specification is particularly good for audio purposes. Check out Wolfson's WM8804 - 100Hz bandwidth.
 
#98
janneman said:
Since this thread seems to be frequented with the jitter cogniocenty (sp?), I'd like to ask your opinion on this new clock clean-up / jitter buster IC from National:

http://www.national.com/an/AN/AN-1734.pdf

Is this something that will help us forward in our search for low jitter DAC recovery clocks?

Jan Didden
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hello Jan,

Let us see:

- communication applications
- lack of crystals

will help you backwards

Communication systems are particularly interested in low jitter at higher frequencies, and fast lock in. Audio needs low jitter from very low frequencies onwards. To achioeve this, you need high Q systems (read crystals) among other things.

best

Guido
 
#100
Guido Tent said:



hello Jan,

Let us see:

- communication applications
- lack of crystals

will help you backwards

Communication systems are particularly interested in low jitter at higher frequencies, and fast lock in. Audio needs low jitter from very low frequencies onwards. To achioeve this, you need high Q systems (read crystals) among other things.

best

Guido
Click to expand...


OK, I wouldn't claim to be a jitter expert (that's you!), but I was impressed by a sub-ns jitter and down to 10Hz loop time constants.
Probably to good to be true.

Jan Didden
 
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