Jitter blocking

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Wavelength

Wavelength

Member
Joined 2004
WavelengthAudio.com
Dustin,

I am presently working with the Crystal CS8421 and would like to see what you have to offer.

I will say the failure of the CS8420 was putting the SPDIF input capability. Man that chip would freak out if you played Linda Ronstant's (sp?) first cd. BelCanto told me that one. There were other customers who told me similar things.

Anyway email me or something as I would like to take a look at it.

Thanks
Gordon
 
Nixie

Nixie

Banned
Joined 2006
Wavelength said:
I will say the failure of the CS8420 was putting the SPDIF input capability. Man that chip would freak out if you played Linda Ronstant's (sp?) first cd.
Click to expand...
That sounds like BS. The last two revisions of the chip had a single, very specific bug in hardware mode that would only occur when locking on to a stream after it was interrupted, and the datasheet explains exactly the type of debug circuit needed (which I implemented and works fine). The program material is irrelevant as to triggering the bug, and would only make a difference as far as how easily the sound of the bug would be audible. Unless that CD had really bad mastering jitter to the point where the ASRC would lose lock (doubt it).
 
Wavelength

Wavelength

Member
Joined 2004
WavelengthAudio.com
Nixie,

NO BS... Several user's of this chip including myself where talked into a deal with Crystal when the part went screwy. I don't want to get into it but in hardware mode the part would do some pretty screwy stuff and all on it's own including:

Filter Cut at 1KHz
Low pass at 4KHz
High pass at 4KHz
Freeze.

This could be fixed if a certain bit in the configuration register was set to 1 to immediately reset the chip. This was also the fix they introduced.

Believe me I had to update every user in the field. It was not pretty and that is why several companies no longer use the chip.

Finnally... yes John president at BelCanto told me in the elevator at the Stereophile show many years ago that they sent Crystal the Linda Ronstandt CD and it made the the chip just stop working altogether.

My problem was that I triggered the mute off the error logic which meant that each time it reset it would click the output.

It was not a good chip in the first place. Many people left Crystal because of this chip and the problems it created internally and with their customers.

Thanks
Gordon
 
Nixie

Nixie

Banned
Joined 2006
Wavelength said:
This could be fixed if a certain bit in the configuration register was set to 1 to immediately reset the chip.
Click to expand...
In hardware mode, one could just use the RST pin, which is what I did. A flip-flop reset after first lock on but not the second time (otherwise it would keep on resetting non-stop), and an NE555 to hold the RST for the minimum time necessary. I posted the simple circuit in 2004 in another thread (rst.png in the attachment at here). It was a pretty simple addition, and with the debugging, the chip worked fine. No need for setting registers with microcontrollers etc.
 
Wavelength

Wavelength

Member
Joined 2004
WavelengthAudio.com
Nixie,

That's not the problem. In the earlier chips the chip would go into these modes and stay there. It had nothing to do with reset stuff. But that is the only way to get around it.

The newer chips actually do a reset if those conditions develop. Yes in the middle of a stream. This is why it is not a good chip to use.

I have thousands of them here that we got as a result of the settlement. Anybody want them I will sell them cheap.

Thanks
Gordon
 
Wavelength

Wavelength

Member
Joined 2004
WavelengthAudio.com
Dustin,

Again I would like to talk too you about your new upsampler.

A few thoughts I had from what you said earlier. First I would not use schmitt triggered inputs. I am no RF engineer but I do work with some and man they hate this stuff. They pretty much bi%%^&^%& up a storm if I even bring them up.

Since I don't know what the SPDIF receiver section includes I may pass on saying anything here. But in my experience having these on the chips with the ARSC is a waste of money. Trying to keep the PLL quiet while you have all that clocking crap going on is a tough trick and better done outside. This is especially true if you are using one of these 27MHZ audio clock generators.

Anyway if you have a draft of a data sheet I would be interested in seeing it.

Thanks
Gordon
 
SSassen

SSassen

Member
Joined 2005
disney.com
Paid Member
Dustin,

Gordon wrote:

A few thoughts I had from what you said earlier. First I would not use schmitt triggered inputs. I am no RF engineer but I do work with some and man they hate this stuff. They pretty much bi%%^&^%& up a storm if I even bring them up.
Click to expand...

I'd have to agree, phase noise seems to be a big issue with these and that's not something you'd want in a SRC, or any other part of a DAC that's concerned with maintaining signal integrity tbh.

Anyway if you have a draft of a data sheet I would be interested in seeing it.
Click to expand...

Me too, as mentioned earlier I have some questions I'd like to ask which go beyond the scope of this forum thread, please PM or email me.

Best regards,

Sander Sassen
http://www.hardwareanalysis.com
 
D

dusfor99

Member
Joined 2006
Nixie said:

That sounds like BS. The last two revisions of the chip had a single, very specific bug in hardware mode that would only occur when locking on to a stream after it was interrupted, and the datasheet explains exactly the type of debug circuit needed (which I implemented and works fine). The program material is irrelevant as to triggering the bug, and would only make a difference as far as how easily the sound of the bug would be audible. Unless that CD had really bad mastering jitter to the point where the ASRC would lose lock (doubt it).
Click to expand...


Very interesting,

I have heard a lot from people about this SPDIF issue, although never experienced it myself. I did however do a side by side test with my ASRC and the CS8421 looses lock with about 50ns of sine jitter added to the SPDIF stream (Tested with APS2) . Then with my ASRC it still maintained lock with up to 400ns since jitter.

Of couse this is sine jitter I guess a better test would be to put white or uniformly distrubeted jitter into it.


CLD
 
D

dusfor99

Member
Joined 2006
Wavelength said:
Dustin,

Again I would like to talk too you about your new upsampler.

A few thoughts I had from what you said earlier. First I would not use schmitt triggered inputs. I am no RF engineer but I do work with some and man they hate this stuff. They pretty much bi%%^&^%& up a storm if I even bring them up.

Since I don't know what the SPDIF receiver section includes I may pass on saying anything here. But in my experience having these on the chips with the ARSC is a waste of money. Trying to keep the PLL quiet while you have all that clocking crap going on is a tough trick and better done outside. This is especially true if you are using one of these 27MHZ audio clock generators.

Anyway if you have a draft of a data sheet I would be interested in seeing it.

Thanks
Gordon
Click to expand...


Hi Gordon,


In the way this ASRC chip works, there is no analog PLL nor is there a PLL that locks to the input SPIDF. Its a purely digital circuit. The chip is entirely in the digital domain so no worries about PLL noise. There are only 3 clocks in the system.

1: The output Sample reate clock (256FS)
2: An internal oversmapling clock to run the FIR filters at about 106Mhz. (This clock can also be outside the chip)
3: In Serial mode, there is the "dclk"




Thanks


Dustin
 
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