As I understand it, becuase in amps with feedback, the whole operation of the circuit is strongly dependant on the operation of the F/B device(s), if this device is changing temperature due to power variations across it caused by the signal then the resultant heating and cooling effects are amplified along with the signal and have a disproportionally high effect in the final performance on an amp.
Almost impossible to assess in spice but one hears that addressing this issue removes a kind of smearing effect on the sound.
that's why I was hoping someone here had done an A/B comparison
I built this feature into my last amp but did not do an A/B
Almost impossible to assess in spice but one hears that addressing this issue removes a kind of smearing effect on the sound.
that's why I was hoping someone here had done an A/B comparison
I built this feature into my last amp but did not do an A/B
AKSA
As a matter of fact I have already gone back from zener to a divider 4.7k/4.7k with an electrolyt 47uF.
Me too, do not want to add zener noise into the circuit.
Or have to counteract such noise.
Bootstrap is an option. It is in line with keeping the amplifier simple.
I will try and see. swordfishy has already tried it in sim.
Okay, Fetzilla, like metal suggested will be the name.
I like the idea of bootstrap.
And Hugh says it could have influence on the harmonics in a good way.
I see you have already tested it in sim.
Hawksford cascode.
It could certainly be an option. If Hugh is positive it can be addded.
My approach is otherwise to keep things simple.
Actually I prefer to go without any cascode.
This is possible with 2SK170 as in my original circuit.
danspy
Sure we, you can try other JFETs.
I shall try to get a hold of 2SK30 spice model.
And see what sdata we can expect.
I see no trouble with using another FET. 2SK246 should work.
Hire is a bigger wan.
*2SK30
*id(R 0.3-0.75 / O 0.6-1.4 / Y 1.2-3.00 / GR 2.6-6.5)
.model J2SK30r NJF(vto=-0.8v beta=0.75m lambda=0 cgd=2.6p cgs=8.2p
+ dev 10% LOT 60%)
.model J2SK30o NJF(vto=-1.1v beta=0.75m lambda=0 cgd=2.6p cgs=8.2p
+ dev 10% LOT 60%)
.model J2SK30y NJF(vto=-1.8v beta=0.75m lambda=0 cgd=2.6p cgs=8.2p
+ dev 10% LOT 60%)
.model J2SK30gr NJF(vto=-2.8v beta=0.75m lambda=0 cgd=2.6p cgs=8.2p
+ dev 10% LOT 60%)
.model J2SK30atm NJF(beta=.768m vto=-2.70 cgd=2.6p cgs=8.2p dev 10% LOT 60%)
* CQ 1988/7
*2SK30
*id(R 0.3-0.75 / O 0.6-1.4 / Y 1.2-3.00 / GR 2.6-6.5)
.model J2SK30r NJF(vto=-0.8v beta=0.75m lambda=0 cgd=2.6p cgs=8.2p
+ dev 10% LOT 60%)
.model J2SK30o NJF(vto=-1.1v beta=0.75m lambda=0 cgd=2.6p cgs=8.2p
+ dev 10% LOT 60%)
.model J2SK30y NJF(vto=-1.8v beta=0.75m lambda=0 cgd=2.6p cgs=8.2p
+ dev 10% LOT 60%)
.model J2SK30gr NJF(vto=-2.8v beta=0.75m lambda=0 cgd=2.6p cgs=8.2p
+ dev 10% LOT 60%)
.model J2SK30atm NJF(beta=.768m vto=-2.70 cgd=2.6p cgs=8.2p dev 10% LOT 60%)
* CQ 1988/7
Lineup,
I like the look of that circuit with the bootstrap VAS!
If this circuit makes less than 1% distortion at 20kHz and 10W in real life I'll be very happy.
Have you noticed with these circuits when simming them that the distortion does not seem to change much between 1W and 20W? This is what I am finding and it is the first amplifier I have simulated and had such a result.
Something I like to do is sim the THD at 20kHz too, as this is when we really start to see the effect of the fet gate capacitance come in to play, and in fact sometime more current in the input and VAS stages may create more distortion at 1kHz but cause significant improvement at 20kHz. I wonder what will prove to be the best compromise?
How did you arrive at 47uF for the bootstrap capacitor? Did you try any other values?
Thanks again, I am enjoying seeing this progress.
I like the look of that circuit with the bootstrap VAS!
If this circuit makes less than 1% distortion at 20kHz and 10W in real life I'll be very happy.
Have you noticed with these circuits when simming them that the distortion does not seem to change much between 1W and 20W? This is what I am finding and it is the first amplifier I have simulated and had such a result.
Something I like to do is sim the THD at 20kHz too, as this is when we really start to see the effect of the fet gate capacitance come in to play, and in fact sometime more current in the input and VAS stages may create more distortion at 1kHz but cause significant improvement at 20kHz. I wonder what will prove to be the best compromise?
How did you arrive at 47uF for the bootstrap capacitor? Did you try any other values?
Thanks again, I am enjoying seeing this progress.
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Hugh,
Still interested, just waiting on parts unfortunately. As soon as they arrive it's back on! I just wish I had ordered more laterals (only got 10 of each)!
Been trying some alternative circuits too which I will post tonight or tomorrow. Think I have found a good compromise between complexity and performance.
Still interested, just waiting on parts unfortunately. As soon as they arrive it's back on! I just wish I had ordered more laterals (only got 10 of each)!
Been trying some alternative circuits too which I will post tonight or tomorrow. Think I have found a good compromise between complexity and performance.
Ahhh, you're going to beat me to it! What is that awesome cad package you're using?
Seeing it laid out like that really illustrates just how simple the circuit is.
Hugh, do you think the lateral fets sold by jaycar are genuine hitachi? If so I might collect some tomorrow and build an incarnation of lineup's circuit with the J201/202/203s I have lying around while I wait for the 2sk170s. Only problem is they aren't great devices, though they are made for audio use and do have a reasonable dissipation rating.
Seeing it laid out like that really illustrates just how simple the circuit is.
Hugh, do you think the lateral fets sold by jaycar are genuine hitachi? If so I might collect some tomorrow and build an incarnation of lineup's circuit with the J201/202/203s I have lying around while I wait for the 2sk170s. Only problem is they aren't great devices, though they are made for audio use and do have a reasonable dissipation rating.
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