Jan,
being content with little, I`m happy to agree with you on those extremely rare occasions.
being content with little, I`m happy to agree with you on those extremely rare occasions.
On what bases is that immediately clear??? What is the purpose of impedance matching and what is actually achieved by impedance matching according to you?
The impedances depend on the physical quantities being transfered.
Now you are denying fundamental physical facts. What is the unconfused difference between frequency dependent time delay and phase shift? Of course, the supposition of zero time delay is standing in the way of a sensible answer.
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http://www.intersil.com/data/an/an9415.pdf
http://www.intersil.com/data/an/an9420.pdf
Amps stable in every way? Now you make me laugh! 99% of the amps across my bench are unstable and very easy to cause oscillation under very simple testing. If amp design was as mature as you suggest this thread would not be needed.
http://www.intersil.com/data/an/an9420.pdf
Amps stable in every way? Now you make me laugh! 99% of the amps across my bench are unstable and very easy to cause oscillation under very simple testing. If amp design was as mature as you suggest this thread would not be needed.
But that's wrong. If I have a system with 50 ohms source and 50 ohms load you lose half the source power.
If you have a 1 ohm source with 100 ohm load you lose 1% power.
jan didden
if you have a 50ohm source and you want maximum power delivery to the receiver then you choose to have a 50ohm load.
If you have a 1ohm source and you want maximum power delivery then you choose a 1ohm load.
If you replace the 1ohm load with a greater value of load then there is less power delivered, i.e. you are not maximising the power delivery.
the Siliconix VMOS metal gate trench fets were used in a few commercial amps - the Japanese also made some metal gate lateral power Fet but both have died out
packaging parasitics would be the real bandwidth limit with those parts
but modern planar Vertical Power MOSFET can be fast enough for low MHz loop gain intercept Audio Power amps
packaging parasitics would be the real bandwidth limit with those parts
but modern planar Vertical Power MOSFET can be fast enough for low MHz loop gain intercept Audio Power amps
I was under the impression (once again, perhaps incorrectly) that the capacitance of each stage the signal passes through results in the phase disparity, and not the delay time.
A suitable cap in the best location (usually at the VAS, to take advantage of the Miller effect) to create a dominant pole will correct the phase.
Yes? No?
Very easy to demonstrate that you are WRONG. Le'ts say your 50 Ohm source has 100 V output . How much power you transfer to load with 50 Ohm : the Max i.e.
(V/2)^2/R =50W.
And now get a BIIIIIG load, say 1000GOhm. How much power you taransfer? Very close to 0. If you want to avoid the calculation try connecting a piece of fiberglass to the output of your ampli, whatever low source impedance you have.
effebi
Actually, what are you guys talking/writing about? transmission losses, maximum power, power dissipated or other things?
Is it RF 50ohm transmission line that need all to be 50ohm to get 1:1 SWR?
Is it RF 50ohm transmission line that need all to be 50ohm to get 1:1 SWR?
jcx,
could it be the VMP11 / VMP12 ? The data sheet specifications suggest a linear transfer characteristic modern planar Vertical Power MOSFET can’t even dream of.
could it be the VMP11 / VMP12 ? The data sheet specifications suggest a linear transfer characteristic modern planar Vertical Power MOSFET can’t even dream of.
For maximum transfer of power, the output impedance must be the same as the input impedance.
For maximum transfer of current, the output impedance and the input impedance must be low.
For maximum transfer of voltage, the output impedance must be low and the input impedance must be high.
Ideal port resistances:
Voltage input - infinite
Current input - zero
Voltage output - zero
Current output - infinite
For maximum transfer of current, the output impedance and the input impedance must be low.
For maximum transfer of voltage, the output impedance must be low and the input impedance must be high.
Ideal port resistances:
Voltage input - infinite
Current input - zero
Voltage output - zero
Current output - infinite
But VAS doesn't need very low (says0.1ohm) output impedance and EF stage must be very high input impedance (10Mohm). There are acceptable condition that VAS could transfer its power to EF stages perfectly (no drop). Like 300ohm VAS output driving 1000 current gain EF for 4ohm load 50Vrms.
There are many condition in transfer power, which one? It is RF that need to be matched to not reflected. Everything in good resonance.
There are many condition in transfer power, which one? It is RF that need to be matched to not reflected. Everything in good resonance.
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I beg to differ sorry.
In order to make some sense, to correclyn model current transfer the source should be modeled as a current generator (i.e. Norton) In such case the output impedance is parallel so the ideal case is High source impedance - low load impedance. I know, is a metter of modeling, but with a series model all the current always flows in the load being only one branch.
effebi
take a power amplifier with an output impedance of 0.1ohms (0r1)
allow that amplifier to present an effective emf of 10Vpk sinewave to the load.
If the load is 100r0 then the Power delivered is [10 / 100+0.1]^2 * 100 / 2 = 0.499W
8r0 load and 6.097W delivered.
1r0 load and 41.32W delivered.
0r5 load and 69.4W delivered.
0r1 load and 125W delivered. If the amplifier and the PSU can pass 50A to the resistive load.
0r05 load and 111.1W. The output power is dropping in the region where the output load drops below the output impedance.
Maximum power delivery occurs when Rload = Rsource
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