well - I really can't remember that I made that comment 
, at least not for F4 .
anyway - A class biased amp is different beast , just because slide of xconductance is much smaller , comparing to sissy B class amps
Ciss/Miller issue is still there , but issue importance is really dependable of circuit and sort of non existent in follower stages
we are always working on compromises
I presume that , for starters , you can ignore gate resistor issue , and just put equal ones . Later - when you are able to find your preferred output stage configuration and type of outputs , then you can proceed in gilding the lily
, at least not for F4 .anyway - A class biased amp is different beast , just because slide of xconductance is much smaller , comparing to sissy B class amps
Ciss/Miller issue is still there , but issue importance is really dependable of circuit and sort of non existent in follower stages
we are always working on compromises
I presume that , for starters , you can ignore gate resistor issue , and just put equal ones . Later - when you are able to find your preferred output stage configuration and type of outputs , then you can proceed in gilding the lily
well - I really can't remember that I made that comment
I could be wrong. Wouldn't be the first or last time.
anyway - A class biased amp is different beast , just because slide of xconductance is much smaller , comparing to sissy B class amps
Ciss/Miller issue is still there , but issue importance is really dependable of circuit and sort of non existent in follower stages
we are always working on compromises
I presume that , for starters , you can ignore gate resistor issue , and just put equal ones . Later - when you are able to find your preferred output stage configuration and type of outputs , then you can proceed in gilding the lily
Will do!
Thanks for the confirmation Jim. I haven't accomplished much the last couple of days other than breaking a tap. Try in to find out how to get it out, I came across a thread where Peter Daniel talked about using a drill to do your tapping. He used a cordless drill with a clutch and lubricant to tap his holes. He claimed it worked great. I didn't believe it till I tried it. I was amazed at how effective and easy it was. A nice bit of info for what is tedious work in my mind. As far as getting a tap out, your basically screwed unless you want to spend a lot of time and effort or just happen to be in a filed where you have access to special tools. I don't, so too bad for me.
well - I really can't remember that I made that comment
Just realized that the pin layout of laterals are different. I love it when things don't work, it keeps me humble and always reminds me to PAY ATTENTION TO DETAIL!!!!!!!!!!!!!!! Let the laughing begin. I was pulling my hair out trying to figure out why things were not working. Hence the obvious questions. Forgot to make sure there was gas in the gas tank
I have encountered something new and I am not positive what it is. After bending Fet legs to fit boards, one channel fired up perfectly and the other I am having a new, never experienced problem. When checking Vds on N vs P fets, the N fets are showing full rail to rail voltage while the P fets are showing about 1V. Does this mean that my P channel fets are blown, passing current as if shorted? Both P and N have enough voltage on gate to be turned on, but very little current is flowing through source resistors.
check them in matching procedure , one by one
convenient praxis , while having fun with expensive Semisouths - put protection zener between source and gate ( as Papa does with mosfets regularly) ;
you can desolder them later , when fun is over .
AR2 burned few , while completing BJ2 , because of , otherwise naive , mistake .
convenient praxis , while having fun with expensive Semisouths - put protection zener between source and gate ( as Papa does with mosfets regularly) ;
you can desolder them later , when fun is over .
AR2 burned few , while completing BJ2 , because of , otherwise naive , mistake .
These were checked and matched all at once before putting them in the amp. They were removed to twist legs, and I am wondering if they were damaged then, or when they were solderd into circuit incorrectly. Everything else in the circuit checks out. Vgs is about .7V, which should put 30-40mA across source resistors, but nothing. DOn't I have to pull the two questionable fets and check them outside the circuit or are you saying to disconnect resistors ( gate and source) and check circuit with one fet hooked up and one not.
Pulled the gate and source resistors for each P channel fet, leaving the other operational
in the circuit. PLugged in bulb tester and fired up channel. Neither fet measured properly showing only 1Vds while N fets are showing 5Vds. I would assume that this means they are both fried offering little to no resistance to current and that is why the majority of the rail voltage is showing up across the N fets. How is my thinking bad, andI know it probably is.
in the circuit. PLugged in bulb tester and fired up channel. Neither fet measured properly showing only 1Vds while N fets are showing 5Vds. I would assume that this means they are both fried offering little to no resistance to current and that is why the majority of the rail voltage is showing up across the N fets. How is my thinking bad, andI know it probably is.
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