I went to Harbor Freight and got myself some largish plastic spring clamps to hold down the outputs on the heat sink, as the usual paper clamps don't work on the larger heat sink I'm using. So, far, it's no-va - I will need to track down possible stuffing or soldering errors, as the outputs don't bias up correctly (read, at all).
OK - I powered up one of the Half Nelson modules I had on hand, and gave it a treatment with a 10kHz square wave and a 7 ohm resistive load. The initial results are shown in the first pic. There is some overshoot. I tried successively larger caps across the 392k resistor from output to the gate of the J175 follower. The amount of capacitance required to clear up the overshoot was quite a bit larger than I suspected it might be, making me think that this might be a sheer drive issue rather than a matter of frequency compensation. This might make me consider changing around the drive to the jfet driving the IRFP240 bottom fet. Anyway, here are the pics. The first pic shows the output for the circuit as-is, without any "compensation". The rise and fall times are nice, but there is a considerable ammount of overshoot. It took about 100pf across the 392k resistor to clean this up, at the cost of a much slower rise time. I tried several values of resistor in series with the cap across the 392k, but the effect on the output square wave wave shape was less than satisfactory.
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New boards with the alternate circuit are winging their way to me (or crawling slowly, from my point of view). The circuit is similar to the 2nd revision of the design, with a little bias on the input p-mosfet to lift it up a trifle. Impedances around the jfet-mosfet Schade pair are also lowered. I'm using a PN4391 as the first stage in the Schade pair, maybe one of the nifty-doodle Linear Systems parts with higher gm and all that. I'll find out when I get around to selecting and characterizing the fets.