Since we are on the subject of reclocking, I made a quick visual sketch of the circuitry on the reclocker board I am using for now with Marcel's dac (the 50R end termination has been disconnected).
The sketch shows one reclocker channel, and some circuitry shared by all channels. In particular there are a number of ceramic caps, ferrite beads, and an inductor in the incoming power filter. There are also ceramic caps used for channel circuitry bypass needs.
The use of ceramic caps and or ferrites is in contrast to what I did in the clock board, and in contrast to the bypassing in my best dac. Looks like ThorstenL also used some SMD film caps for the DSD dac he designed for iFi (there is a pic of the board in the Marcel DSD FIRDAC thread).
In consideration of the above, I would probably not use this particular reclocker circuitry if I wanted to try to get the best possible reclocking. Most of it looks okay, except for the items mentioned above. IIUC this reclocker board is an older design that was used with some earlier IC dac. I got a couple of the reclocker boards mainly to try with the Acko version of Marcel's DAC I had here previously. Anyway thinking about it a little more now, maybe there would be some justification for designing a new reclocker board. Don't know if I want to be the volunteer though.
The sketch shows one reclocker channel, and some circuitry shared by all channels. In particular there are a number of ceramic caps, ferrite beads, and an inductor in the incoming power filter. There are also ceramic caps used for channel circuitry bypass needs.
The use of ceramic caps and or ferrites is in contrast to what I did in the clock board, and in contrast to the bypassing in my best dac. Looks like ThorstenL also used some SMD film caps for the DSD dac he designed for iFi (there is a pic of the board in the Marcel DSD FIRDAC thread).
In consideration of the above, I would probably not use this particular reclocker circuitry if I wanted to try to get the best possible reclocking. Most of it looks okay, except for the items mentioned above. IIUC this reclocker board is an older design that was used with some earlier IC dac. I got a couple of the reclocker boards mainly to try with the Acko version of Marcel's DAC I had here previously. Anyway thinking about it a little more now, maybe there would be some justification for designing a new reclocker board. Don't know if I want to be the volunteer though.
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Hi Mark & @bohrok2610 ...
Thank you both for considering & replying to my post above. I actually didn't intend to open this subject too much on my own behalf - just sharing the thoughts and immediate experiences I have had with considering reclocking options. As it is I think it will be too comprehensive for me at this point in time to actively participate in such a development but if you decide to progress, Mark, with the design of yours I will be following it "on the side" so to speak. Hope that is ok ...
As to your question about the spectrum analyzer, I am using a very basic device, the TinySA (not the Ultra), which as far as I can see is not an SDR spectrum analyzer ..? Also, as far as I can see, the reviews on the internet appear to recognize it as being a quite reliable device although with slightly less resolution (and possibly features) than dedicated spectrum analyzers.
But I guess it makes sense that this may/might be a case of aliasing - yet the upper frequency limit is around 250 MHz in the setting I use ... so could aliasing be present with 2.8 MHz intervals when the DSDCLK is at this frequency .. ?? There is no chance that somehow the reference clock and the BCLK/DSDCLK to be reclocked "multiply" or "overlay" each other? The phenomenon was completely obvious on the TinySA - no noise signals or the like in-between frequency pins ...
Cheers, Jesper
Thank you both for considering & replying to my post above. I actually didn't intend to open this subject too much on my own behalf - just sharing the thoughts and immediate experiences I have had with considering reclocking options. As it is I think it will be too comprehensive for me at this point in time to actively participate in such a development but if you decide to progress, Mark, with the design of yours I will be following it "on the side" so to speak. Hope that is ok ...
As to your question about the spectrum analyzer, I am using a very basic device, the TinySA (not the Ultra), which as far as I can see is not an SDR spectrum analyzer ..? Also, as far as I can see, the reviews on the internet appear to recognize it as being a quite reliable device although with slightly less resolution (and possibly features) than dedicated spectrum analyzers.
But I guess it makes sense that this may/might be a case of aliasing - yet the upper frequency limit is around 250 MHz in the setting I use ... so could aliasing be present with 2.8 MHz intervals when the DSDCLK is at this frequency .. ?? There is no chance that somehow the reference clock and the BCLK/DSDCLK to be reclocked "multiply" or "overlay" each other? The phenomenon was completely obvious on the TinySA - no noise signals or the like in-between frequency pins ...
Cheers, Jesper
EDIT OF EARLIER POST: Looking at Tiny SA again and in more depth, they say it does include anti-aliasing up to 350MHz. https://tinysa.org/wiki/pmwiki.php?n=Main.TechnicalDescription
Don't know the filter technical details though -- how much attenuation in the stop band, etc.
Its also possible for spectral peaks to be due to overloading the inputs: https://tinysa.org/wiki/pmwiki.php?n=Main.ATTENUATION
Don't know the filter technical details though -- how much attenuation in the stop band, etc.
Its also possible for spectral peaks to be due to overloading the inputs: https://tinysa.org/wiki/pmwiki.php?n=Main.ATTENUATION
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Mark ... thanks for the follow-up. I think I will make a couple of screen-dumps possibly tomorrow to show what I mean. I reckon it may be easier to see what is going on than just talking about it (and, really, you don't have to be interested in this - I just thought it was an odd phenomenon).
Have a fine evening when you get thus far,
Jesper
Have a fine evening when you get thus far,
Jesper
A couple of updates. First, version 2 prototype clock boards are on their way from jlcpcb. ETA is Thursday.
Second thing is just did a little experiment with the reclocker board presently used here with Marcel's dac. Bypassed most of the existing power filter and added a 10uf Rubycon SMD film cap at the filter output. Sound of the audio has definitely changed. A lot of the remaining little bit of HF fuzzzz that was evident in the dac sound is replaced by what sounds smoother and not so fuzzy, maybe like a little more signal correlated 1/f noise. Some of that apparent noise is probably from taking down the dac for a couple hours which let the clocks cool off. That particular part of noise seems to be receding as the dac runs for a few hours after coming back up. The little bit of fuzziness hasn't come back through, not yet anyway.
Anyway, main thing is that existing power filter processing and bypass design of the reclocker board is affecting the dac sound, and doing so in a way that I don't believe can be right. Thus, looking more and more like a new reclocker design will be needed. Aside from power filtering and or bypass changes, maybe a few opportunities for alternate layout details could end up being helpful too. Have to try it and see.
Second thing is just did a little experiment with the reclocker board presently used here with Marcel's dac. Bypassed most of the existing power filter and added a 10uf Rubycon SMD film cap at the filter output. Sound of the audio has definitely changed. A lot of the remaining little bit of HF fuzzzz that was evident in the dac sound is replaced by what sounds smoother and not so fuzzy, maybe like a little more signal correlated 1/f noise. Some of that apparent noise is probably from taking down the dac for a couple hours which let the clocks cool off. That particular part of noise seems to be receding as the dac runs for a few hours after coming back up. The little bit of fuzziness hasn't come back through, not yet anyway.
Anyway, main thing is that existing power filter processing and bypass design of the reclocker board is affecting the dac sound, and doing so in a way that I don't believe can be right. Thus, looking more and more like a new reclocker design will be needed. Aside from power filtering and or bypass changes, maybe a few opportunities for alternate layout details could end up being helpful too. Have to try it and see.
Hi Mark,
A brief update on the spectrum analyzer and the multiplying frequencies I had observed relative to the sample frequency used: I repeated the measurements this morning and - fortunately - it seems there must have been some kind of error in the previous measurements I made
...
I really have no idea how this could happen as I checked the results several times (because they were surprising) ... But nevertheless apparently an error. Now everything measures as I would expect it to, so ... thanks Mark for pointing out this "multiplying mistake" 🙏 ... A very good thing to have it cleared from the "experience box".
BTW with respect to ferrite beads: My experience is that, yes, they do isolate different domains of e.g. digital circuitry but they also "encage" these circuitries. Thus, using e.g. a 100nF decoupling capacitor on the IC side of a ferrite bead (i.e. ferrite bead, 100 nF, VDD of IC) IME likely gives substantial noise levels on the IC VDD pin. But I reckon you already know this ...
Cheers & thanks again! ... Jesper
A brief update on the spectrum analyzer and the multiplying frequencies I had observed relative to the sample frequency used: I repeated the measurements this morning and - fortunately - it seems there must have been some kind of error in the previous measurements I made
...I really have no idea how this could happen as I checked the results several times (because they were surprising) ... But nevertheless apparently an error. Now everything measures as I would expect it to, so ... thanks Mark for pointing out this "multiplying mistake" 🙏 ... A very good thing to have it cleared from the "experience box".
BTW with respect to ferrite beads: My experience is that, yes, they do isolate different domains of e.g. digital circuitry but they also "encage" these circuitries. Thus, using e.g. a 100nF decoupling capacitor on the IC side of a ferrite bead (i.e. ferrite bead, 100 nF, VDD of IC) IME likely gives substantial noise levels on the IC VDD pin. But I reckon you already know this ...
Cheers & thanks again! ... Jesper
Do you mean there is more "engagement" with ferrite bead than without (i.e. with direct connection)?
LMK1C110x datasheet chapter 11 gives general guidelines on clock buffer power supply.
IIUC, Jesper quoted "encage" because its a made-up word. Presumably means to enclose something in a cage.
If so, then we have two suggested mechanisms for why ferrites might be implicated in noise problems.
In any case, LMK1C110x is designed to be used in applications up to 250MHz. That's way above what we would usually use for audio. Also, doubtful there a lot of clock buffer chips sold for digital audio use. Thus, some recommendations in datasheets may be directed at customer applications that use thousands and thousands of chips. Maybe multiplexed RF communications, or other things rather removed from hi-fi audio down around 22/24MHz or so. For typical applications, and especially with very high frequency clocks, seems likely datasheets are giving reasonable advice.
However and IME for digital audio and at lower clock frequencies like we are using here, what works best is not necessarily what the ferrite bead seller guys are hoping we will buy. If we are careful we can make sure the power is pretty clean on a clock board running at a few 10s of MHz without having to use ferrites in the process.
Its a whole 'nother ballgame maybe up around 100MHz and beyond, especially if fastest possible risetimes are needed, and maybe for something like a densely packed digital radio board.
Those are my thoughts at the moment anyway.
If so, then we have two suggested mechanisms for why ferrites might be implicated in noise problems.
In any case, LMK1C110x is designed to be used in applications up to 250MHz. That's way above what we would usually use for audio. Also, doubtful there a lot of clock buffer chips sold for digital audio use. Thus, some recommendations in datasheets may be directed at customer applications that use thousands and thousands of chips. Maybe multiplexed RF communications, or other things rather removed from hi-fi audio down around 22/24MHz or so. For typical applications, and especially with very high frequency clocks, seems likely datasheets are giving reasonable advice.
However and IME for digital audio and at lower clock frequencies like we are using here, what works best is not necessarily what the ferrite bead seller guys are hoping we will buy. If we are careful we can make sure the power is pretty clean on a clock board running at a few 10s of MHz without having to use ferrites in the process.
Its a whole 'nother ballgame maybe up around 100MHz and beyond, especially if fastest possible risetimes are needed, and maybe for something like a densely packed digital radio board.
Those are my thoughts at the moment anyway.
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Yes, from DC to 250MHz. This covers audio clock frequencies as well. Also the power supply recommendations in the datasheet have no frequency dependence.
@bohrok2610 :
No, I mean "box-in" as if the ferrites confines the signals on either side of the ferrite (encage definition e.g. here: https://www.dictionary.com/browse/encage ). Which I reckon is the intention but IME it also means that unless the decoupling on the VDD side of the ferrite is quite extensive the noise levels on the VDD pin are high(er).
I tend to lean towards separate supplies for critical circuitry or, like Marcel does it in the RTZ DAC, to have multiple decouplings in a circuitry "group" which is then isolated from other circuitry "groups" with ferrites or inductors.
It would be great some day to be able to measure how the actual decoupling affects something like phase noise. Currently simulation, intuition and best guesses are the tools I can use - which often is fine but in this case I wouldn't mind being able to supplement with some measured results.
Cheers, Jesper
No, I mean "box-in" as if the ferrites confines the signals on either side of the ferrite (encage definition e.g. here: https://www.dictionary.com/browse/encage ). Which I reckon is the intention but IME it also means that unless the decoupling on the VDD side of the ferrite is quite extensive the noise levels on the VDD pin are high(er).
I tend to lean towards separate supplies for critical circuitry or, like Marcel does it in the RTZ DAC, to have multiple decouplings in a circuitry "group" which is then isolated from other circuitry "groups" with ferrites or inductors.
It would be great some day to be able to measure how the actual decoupling affects something like phase noise. Currently simulation, intuition and best guesses are the tools I can use - which often is fine but in this case I wouldn't mind being able to supplement with some measured results.
Cheers, Jesper
Sorry, I misunderstood your meaning. Yes, the purpose of ferrites is to isolate critical circuitry to avoid mixing different noise sources. But e.g. on a MCK clock buffer the dominant noise source is quite likely MCK and the ferrite does not change that and anyhow at MCK frequencies local decoupling is more important than regulator. I use separate low noise regulators for clock circuitry in my dacs and adcs but I still use ferrites to separate MCK clock buffer from e.g. I2S buffers.
Regarding ferrites, they may not all be bad. There are many types of ferrite material. There are magnetically soft and hard ferrites, which have differently shaped B-H curves, etc. Only way to know if particular ferrites are causing problems with a particular circuit is to do some testing. Spectral analysis may or may not be useful. Even if it shows something, it can't be known how what it shows is related to the peak magnitude of the noise. It may be very loud pops yet look like a smooth noise floor. IOW, it can be one of those cases where phase can cause peak noise to exceed the threshold of audibility of group delay for the noise (or more or less the equivalent of that). Which is to say there is only so much noise power. If its expended all at once it can make a loud pop noise. That is despite whether it is white noise or colored. Its also not all that related to what the average noise power shown in spectral analysis is.
Probably going to take a few days for the new board to fully settle in, so it will be running most hours of the day to get some time on it.
One interesting thing about LMK1C1104, the clock buffer chip used in this 2nd prototype version of the board, is that the datasheet says source series resistors can be used to match it to the load impedance being driven, but the output impedance of buffer itself is given as 50-ohms. Does seem like it might be driving the reclocker board a little better with no series damping resistor.
OTOH, the buffer used in the first prototype, NB3L553-D, seems to work clearly better with at least a minimal source series termination resistor.
Once the board is settled in, probably should do some scope measurements of the clock waveforms with different damping resistors. We'll see.
Also, there is a bit of a pop noise when and if clock frequencies are changed between songs. Using the mute signal going into the dac board may not fully accomplish an effective mute if the dac is operating in SE mode. That may be because when a mute occurs the dac output does not go to zero in the SE sense (Vref/2), rather it may go to ground.
One interesting thing about LMK1C1104, the clock buffer chip used in this 2nd prototype version of the board, is that the datasheet says source series resistors can be used to match it to the load impedance being driven, but the output impedance of buffer itself is given as 50-ohms. Does seem like it might be driving the reclocker board a little better with no series damping resistor.
OTOH, the buffer used in the first prototype, NB3L553-D, seems to work clearly better with at least a minimal source series termination resistor.
Once the board is settled in, probably should do some scope measurements of the clock waveforms with different damping resistors. We'll see.
Also, there is a bit of a pop noise when and if clock frequencies are changed between songs. Using the mute signal going into the dac board may not fully accomplish an effective mute if the dac is operating in SE mode. That may be because when a mute occurs the dac output does not go to zero in the SE sense (Vref/2), rather it may go to ground.
Turns out even though LMK1C1104 has an output impedance of 50-ohms according to the datasheet, it doesn't appear to work all that well to dampen/terminate an otherwise unterminated line. With a 33-ohm source series resistor, the buffer seems to be working satisfactorily (haven't done a search to see if there is a more optimal value).
With that, I think this version of board will be fine for whatever little bit is left to do. Next up is to add a frequency multiplier.
Sometime after that I will take a look at what might be done for a reclocker board (since nobody else has volunteered, at least not yet).
With that, I think this version of board will be fine for whatever little bit is left to do. Next up is to add a frequency multiplier.
Sometime after that I will take a look at what might be done for a reclocker board (since nobody else has volunteered, at least not yet).
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Put together a couple squaring boards, plus salvaged an old frequency multiplier to run the next experiment:
However, will use the 2nd prototype clock board with the other buffer chips. Also, looks like the squarers include ferrite beads. I may try the boards with and without the ferrites to just to see if any noticeable difference.
However, will use the 2nd prototype clock board with the other buffer chips. Also, looks like the squarers include ferrite beads. I may try the boards with and without the ferrites to just to see if any noticeable difference.
Hi Mark ... Still thinking that it looks neat your board ... Regarding the ferrites & the squarer board it is my experience that the noise level on the inside of the ferrite, i.e. towards the VDD pin, is (very) high. My personal guess is that it likely affects the squaring function but since I don't yet have a phase noise measuring device I cannot confirm this ...
BTW it looks as if you use quite a bit of Rubycon MU (or similar?) decoupling capacitors ... Have you tried to measure their impedance & inductance? As far as I can measure and see from Rubycon's white paper on these capacitors, both inductance and impedance levels are high .. So my thinking is that they may not be very efficient in actually decoupling/damping the switching noise. Might you have any observations on this?
Cheers, Jesper
... Regarding the ferrites & the squarer board it is my experience that the noise level on the inside of the ferrite, i.e. towards the VDD pin, is (very) high. My personal guess is that it likely affects the squaring function but since I don't yet have a phase noise measuring device I cannot confirm this ...BTW it looks as if you use quite a bit of Rubycon MU (or similar?) decoupling capacitors ... Have you tried to measure their impedance & inductance? As far as I can measure and see from Rubycon's white paper on these capacitors, both inductance and impedance levels are high .. So my thinking is that they may not be very efficient in actually decoupling/damping the switching noise. Might you have any observations on this?
Cheers, Jesper