metalman: Thank you for the feedback!
Somewhere between my posts and today (which included reading the AN1192 note a few more times) I realized that the Cin cap value critical point was making sure they weren't too small.
NS uses .47uF in their BPA200 circuit. 😉
The 0.1Ω output resistor values are straight out of the BPA circuit. I'll pick up some extras to give me some range.
I believe I may also simply build a buffer (using the same NPN as the rest of the circuit - Nuuk has a simple one on his site and he reports good results with it) prior to a DRV134 that I can use. Simple because it can run off the same 15-18V +/- power.
I'm realizing this will also be a somewhat (relatively speaking) power hungry setup going with standard chip-amp practice. Might make regulated power mandatory for all but the most insane.
Getting closer to a point where building this might be do-able. 🙂 Too many projects going still. Slow but sure they get done (warm enough weather on weekends for wood finish and glue to work properly helps).
C
Somewhere between my posts and today (which included reading the AN1192 note a few more times) I realized that the Cin cap value critical point was making sure they weren't too small.
NS uses .47uF in their BPA200 circuit. 😉
The 0.1Ω output resistor values are straight out of the BPA circuit. I'll pick up some extras to give me some range.
I believe I may also simply build a buffer (using the same NPN as the rest of the circuit - Nuuk has a simple one on his site and he reports good results with it) prior to a DRV134 that I can use. Simple because it can run off the same 15-18V +/- power.
I'm realizing this will also be a somewhat (relatively speaking) power hungry setup going with standard chip-amp practice. Might make regulated power mandatory for all but the most insane.
Getting closer to a point where building this might be do-able. 🙂 Too many projects going still. Slow but sure they get done (warm enough weather on weekends for wood finish and glue to work properly helps).
C
dieringe said:
A cap across the feedback doesn't work here.
The chip is not stable at unity gain.
My theory on the problem is that the phase margin of the circuit starts to increase above 20kHz, and rapidly increases above 100kHz The resulting phase lag between the input signal and feeback signal causes a high frequency bump in gain (+0.5dB at 100kHz, peaking at +2dB around 500kHz).
Carlos's comment is a gross oversimplification, but points in the right direction, namely that the 68pF value is definitely too large. It results in an increase in feedback level by ~0.5dB at 30kHz. The trick is to choose the capacitor value so that the ultrasonic bump is attentuated without increasing the feedback level within the audioband. The circuit as I've posted it is right near the boundary of stability, so any increase in feedback level within the possible input signal bandwidth will cause the circuit to begin oscillating, causing exactly the overheating and shutdown that you have described. In fact you've just quantified exactly how close the the stability limit the circuit is. Bravo, and great work!
A 20pF cap value results in a feedback increase of 0.5dB at 70kHz, and a 10pF cap puts the 0.5dB point out to 110kHz. In retrospect, the 10pF value is probably best, as it pushes the feeback increase beyond the audioband which should prevent the circuit from going into oscillation (I hope). Please note that I am basing most of this on calculations and I haven't had a chance to directly experiement with this yet.
Lastly, we can simultaneously address both sides of this equation: throw away some more gain, reduce the overall feedback and add the extra caps. This increases the available margin to increase the feedback at high frequencies via the additional caps. Rough estimate for this would be increase R3 and R4 to 20kohm, increase R7 and R8 to 65kohm, and make the caps parallel to R7 and R8 10picofarad.
Dieringe, thanks for posting your experiment results. Your participation has produced a significant contribution in refining this project.
Cheers, Terry
Yeah, but those boys at NS think that -3dB at 20Hz is good enough. In the XGC case, 0.47uF will cause -3dB to be at ~30Hz. 4.7uF puts the -3dB point at 3Hz. With 10uF caps in my circuit, the -3dB point is under 2Hz.
Go cjd! I've got a similar idea simmering on the backburner, except that I'm bootstrapping the extra op-amps instead of paralleling them. My current XGC version begins to whimper if driving anything with an impedance dip below 4 ohms (luckily my speakers min impedance is only 6). But I'd love have a version that could tackle some Thiel or Wilson Audio type speakers. I forgot to mention in my earlier post that otherwise I think you've got your circuit to the point where your next best effort will be to build it and see what happens! You've got me curious.
Cheers, Terry
Just a smidge under 32dB closed loop.
Edit: I should mention that I still haven't got around to snubbing my powersupply, but it is definitely onm my list. Great work you did there!
In my original design I was shooting for 24dB, but because the open loop gain of these chips is so high, the necessary feedback to keep it at that closed loop gain level just sent the amp into wild oscillation.
One answer was to add degeneration to the differential pair to reduce its gain, but that also reduces the supersymmetry effect, which defeats the whole point of the design, so I ignored that option.
Another answer was to throw away gain between the differential pair and the chips, but by the time I had tossed enough gain to keep the amp stable at 24dB gain, the signal being fed to the chip inputs was getting pretty miniscule.
My last resort was to increase the closed loop gain to bring the input signal at the chips back to some decent level.
In retrospect, I think that what you suggest could be achieved, probably by increasing R3 and R4 to around 50k, but I am skeptical that there would be any sonic improvement. Then again, I probably shouldn't speculate without trying it first. Hmm...
Actually you'd have to leave R3 and 4 at 20K and change r9 and R10 to 400ohms. A little play time might be in order.
dieringe,
My discussion with Carlosfm made me think about thinks a little differently and inspired a different implementation of this same idea that might work better.
Instead of putting 10pF caps in parallel to R7 and R8, put ~1nF caps in parallel with R9 and R10. This should reduce the high frequency bump by reducing high frequency gain without fiddling with the feedback levels.
Just a thought.
My discussion with Carlosfm made me think about thinks a little differently and inspired a different implementation of this same idea that might work better.
Instead of putting 10pF caps in parallel to R7 and R8, put ~1nF caps in parallel with R9 and R10. This should reduce the high frequency bump by reducing high frequency gain without fiddling with the feedback levels.
Just a thought.
dieringe said:
I suspect a series RC network in parallel with the feedback resistor could be made to work, but the passive filtering Terry suggested seems like it would be the better route.
dieringe said:
It's inversely porportional. x10 in cap size, /10 in frequency. So you have a cap that is ~20% of 4.7uF so take 3Hz / .2 = 15 Hz. This checks because it's about double .47uF or half of 30Hz = 15Hz.
The real equation is to look at the input node of the circuit and calculate all apparent resistances to gnd and all apparent capacitance to gnd. Fc = 1/(2*pi*R*C) Which is where you can see the inverse porportionality.
--
Danny
The method I was using is a rough off-the-cuff calculation based on the following. The voltage signal reduction between the differential pair and the chips is
R9/(R9+R3+Z(C1)) where Z(C1) is the frequency dependant impedance of C1 that is calculated as:
Z(C) = 1/(2*pi*f*C)
The -3dB point occurs approximately where R3 = Z(C1), so we can rearrange to get:
f(-3dB) = 1/(2*pi*C*R3)
Using this calculation, 1uF places -3dB at ~15Hz.
The drawback to this rough calculation method is that it ignores the effect of the feedback loop at the differential pair, which will act to correct the low frequency roll-off, moving the -3dB point to a lower frequency. The easiest way to identify this effect is to spice model the circuit and try different capacitance values, which I did last night. The results were:
0.47uF: -1dB at 11Hz, -3dB at 6Hz
1.00uF: -1dB at 6Hz, -3dB at 3Hz
While I was at it, I simulated using caps paralleled with R9 and R10, and the results were no good. The caps at those locations just increase the phase lag at high frequency and make the ultrasonic bump even worse.😱
Back to the drawing board ... let me think on this some more.
Terry
Out of curiousity, have you tried lowering the rail voltage?
For a bridged pair of 3886 chips, NA is recommending a maximum rail voltage of 20V for 4ohm, 24V for 6ohm, and 28V for 8ohm. 28V looks about good for 4ohm speakers on a BPA setup.
Of course, this only becomes more critical as things are driven hard IIRC.
Trying to source transformers in the size and voltages I want at the moment. 🙂 May end up just having one wound 22V 1000VA / 15V 100VA.
C
For a bridged pair of 3886 chips, NA is recommending a maximum rail voltage of 20V for 4ohm, 24V for 6ohm, and 28V for 8ohm. 28V looks about good for 4ohm speakers on a BPA setup.
Of course, this only becomes more critical as things are driven hard IIRC.
Trying to source transformers in the size and voltages I want at the moment. 🙂 May end up just having one wound 22V 1000VA / 15V 100VA.
C
Hmmm ... very interesting ...
Carlos, could I entice you to share your reasoning for choosing 27dB.
metalman said:
These chips work (and sound) better at gains of between 20~22x.
That's my experience.
Less noise (hiss) also, as it starts to be evident at gains of above ~35x.
Better use a gainstage before the chip if one needs more gain (like when making an integrated amp).
This points to a conclusion that the chip is, of course, a power amp and needs a pre.😀
I was not commenting specifically on the topology you are testing, it's just that the chip sounds better at lower gains.
metalman said:
I hope this is correct, then I could throw out the electrolytics and use 1µF foils instead.
Lowering gain: 1 or 2 pages before you said you could change R3/R4 "from 20k" to something else. They are 10k in your schematic...?
How would I lower gain? Less would be sufficient and I suspect you get better sound and maybe it helps the sharpness problem...
m.
Well, your subjectivism is remarkably accurate within an objectivist analysis! I played around with the idea of further gain reduction, and this brightness (AKA ultrasonic bump) perfectly flattens out at a closed loop gain of 26.5dB, or it does in the simulation at least. You have some fine ears!
It sure looks that way to me!
You're right, I misquoted. R3/R4 are 10K and should be left that way. Change R9/R10 to 220 ohm to get 26.5dB gain (down from 32dB). According to the sims this should iron out the brightness to a fair degree.
Here's hoping it works in real life the way it does simulation.
Cheers, Terry