That's true enough. I don't know how you can fault the package for that. This would seem to be an intentional way of destroying the part if you ask me.
I have bent a few leads and carefully straightened them back up with no ill effects.
-Chris
I have bent a few leads and carefully straightened them back up with no ill effects.
-Chris
I'm not faulting the package.
Just comparing that it's harder to do this to a TO220.
If you look up the properties of glass you'll see it's not as resistent to stress as epoxy.
My only point was that some care is required in handling the TO3.
You dont have to take that advice; you are free to abuse it as you wish.
Just comparing that it's harder to do this to a TO220.
If you look up the properties of glass you'll see it's not as resistent to stress as epoxy.
My only point was that some care is required in handling the TO3.
You dont have to take that advice; you are free to abuse it as you wish.
vectorplane said:
Question for anyone who has cracked open flat packs (TO220, 247, 264):
Is the top face of the die in direct contact with the epoxy molding material, or is there a small space of air above it?
Hi vectorplane - I'm late into the discussion - again. Why the question anyway? You looking at extra capacitance due to the epoxy?
One of the problems with epoxy is actually bending of the gold wires, causing shorts. This is caused by the plastic not quite being liquid enough as it is injected and molded. So, the stuff definitely gets into contact with the silicon and would be out-of-norm to have voids...
Cheers!
Clem
Hi Vectorplane,
I don't think epoxy would survive that test either in the same mechanical configuration. Epoxy packages have their own issues, so I think you simply have to be aware of the issues with whatever package you are using.
This is a bit O.T. anyway.
-Chris
I don't think epoxy would survive that test either in the same mechanical configuration. Epoxy packages have their own issues, so I think you simply have to be aware of the issues with whatever package you are using.
This is a bit O.T. anyway.
-Chris
Clem:
Do you still need to pursue a uC solution?
Or are you ok with using a capacitince meter.
The question about epoxy voids was to determine if an additional heatsink placed on TOP of the flatpack could in some cases be implemented for enhanced heat removal from the die.
(ie. sandwich the flatpack between 2 heatsinks)
Andy
Do you still need to pursue a uC solution?
Or are you ok with using a capacitince meter.
The question about epoxy voids was to determine if an additional heatsink placed on TOP of the flatpack could in some cases be implemented for enhanced heat removal from the die.
(ie. sandwich the flatpack between 2 heatsinks)
Andy
Hi Andy,
There would be problems with the leads that attach to the die. They are attached from the top "flying" as it were. When you crack a transistor apart, these normally leave with the top encapsulation.
-Chris
There would be problems with the leads that attach to the die. They are attached from the top "flying" as it were. When you crack a transistor apart, these normally leave with the top encapsulation.
-Chris
OT: encapsulation voids
😕 😕
Chris, I'm not sure which question you're addrssing.
If there are no voids in the epoxy, it means that both sides of the flatpack can be used to conduct heat away.
For any given heat sink arrangement, anytime you want to add an additional 5 square inches of heat sink, it's better to add it close to the device, than at the extremity of an existing heat sink.
But if there is a void inside the epoxy, than removing heat through the top face becomes less attractive.
The above might be relevant only if you need to minimize thermal resistance(case-to-ambient) in a space-constrained application.
Again, sorry for the OT.
Andy
anatech said:Hi Andy,
There would be problems with the leads that attach to the die. They are attached from the top "flying" as it were. When you crack a transistor apart, these normally leave with the top encapsulation.
-Chris
😕 😕
Chris, I'm not sure which question you're addrssing.
If there are no voids in the epoxy, it means that both sides of the flatpack can be used to conduct heat away.
For any given heat sink arrangement, anytime you want to add an additional 5 square inches of heat sink, it's better to add it close to the device, than at the extremity of an existing heat sink.
But if there is a void inside the epoxy, than removing heat through the top face becomes less attractive.
The above might be relevant only if you need to minimize thermal resistance(case-to-ambient) in a space-constrained application.
Again, sorry for the OT.
Andy
Hi Andy,
Sorry for being ambiguous. I was answering
You would be further ahead to contact the heatsink around the device and provide more surface area on the top side too. That is sometimes seen.
-Chris
Sorry for being ambiguous. I was answering
Although not very clearly.The question about epoxy voids was to determine if an additional heatsink placed on TOP of the flatpack could in some cases be implemented for enhanced heat removal from the die.
You would be further ahead to contact the heatsink around the device and provide more surface area on the top side too. That is sometimes seen.
-Chris
vectorplane said:
Do you still need to pursue a uC solution?
Or are you ok with using a capacitince meter.
The question about epoxy voids was to determine if an additional heatsink placed on TOP of the flatpack could in some cases be implemented for enhanced heat removal from the die.
(ie. sandwich the flatpack between 2 heatsinks)
Hi Andy - I'm certainly fine with using a capacitance meter - but I do have to check if my unit is up to it (many things seem to have gotten in the way this weekend)...
re: additional heatsink on top of a flatpack - I don't remember the specs from sumitomo plastics, but had the impression that the thermal resistance wasn't that good. The only reason the top gets hot "faster" than the rear is the low thermal mass, so it will probably help only a little...
Cheers!
Clem
Hi Clem,
Does that mean you get to play in the lab with various transistors and a cap checker?
-Chris
Does that mean you get to play in the lab with various transistors and a cap checker?
-Chris
Hi Chris,
I used to work for Zilog actually, 1st job, was a test engineer. So, not transistors, but much more integrated stuff... Every time one of the Z80 yields went down it was a bad day for me... 🙂
These days, the labs at the uni are more oriented to really basic stuff, so I actually get to 'play' more with the equipment I have at home...
Cheers!!
Clem
I used to work for Zilog actually, 1st job, was a test engineer. So, not transistors, but much more integrated stuff... Every time one of the Z80 yields went down it was a bad day for me... 🙂
These days, the labs at the uni are more oriented to really basic stuff, so I actually get to 'play' more with the equipment I have at home...
Cheers!!
Clem
Hi Clem,
Shhhh! Not in public! You're (carbon) dating yourself! 😉
Sounded like fun, except when the process was not in control.
-Chris
Shhhh! Not in public! You're (carbon) dating yourself! 😉
Sounded like fun, except when the process was not in control.
-Chris
Hi Chris - haha, well, does it help to say that the product line was very very old already when they put me on it?! 🙂
Cheers!
Clem
Cheers!
Clem
Hi Clem,
Nope - sorry.
By that time the yields were generally much better, or was that your doing? 😉
Do you have any evil Intel stories for us?
-Chris
Nope - sorry.

By that time the yields were generally much better, or was that your doing? 😉
Do you have any evil Intel stories for us?
-Chris
Andy,
Googled around and of course it turns out that there are several manufactured versions of the epoxy mold with varying thermal resistance... Info seems to be a bit sparse, but there's one report that mentions junction-to-case resistance to be 8.9 degC/Watt, tested on an IC packaged as a QFP.
Cheers!
Clem
Googled around and of course it turns out that there are several manufactured versions of the epoxy mold with varying thermal resistance... Info seems to be a bit sparse, but there's one report that mentions junction-to-case resistance to be 8.9 degC/Watt, tested on an IC packaged as a QFP.
Cheers!
Clem
anatech said:Hi Clem,
Nope - sorry.![]()
By that time the yields were generally much better, or was that your doing? 😉
Do you have any evil Intel stories for us?
Hi Chris,
Unfortunately(?) the Philippines only does packaging and final test, hardly any reason for yields to be low, unless something really goes wrong! And when it does go wrong, all hell breaks loose, of course. Usually its a bad test machine, and hell yeah I have a lot of stories about that, getting into the innards of those ancient beasts. Didn't wind up with the big "I", but I don't think there's anything to regret... 🙂
Cheers!
Clem
Most of the heat is going down the leads, don't count on much going through the epoxy. TO-220 devices should be mounted with the shoulder on the leads flush to the ads and use as fat pads and tracks as possible.
Hi davidsrsb,
I wouldn't expect much heat transfer via the emitter and base leads, as it's a thin piece of wire that connects those to the die?
Cheers!
Clem
I wouldn't expect much heat transfer via the emitter and base leads, as it's a thin piece of wire that connects those to the die?
Cheers!
Clem
Yes, most of the heat comes off the collector to the tab. The collector lead will get hot, but it won't be much help. If you are free air mounting, the collector lead is where most of the heat is.
Clem, did you get the wafers to break and mount, or not even? (ever play frisbee with one?
)
-Chris
Clem, did you get the wafers to break and mount, or not even? (ever play frisbee with one?

-Chris
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