There is none in the measurement range. The FR plot is flat, no energy is stored within 20Hz-20kHz. Next to that I tried a 20 kHz blockwave, which looked just fine. I think my results aren't half bad. I just wondered where to look for improvement. I think the first steps should be testing with a nicer PSU and changing my signal cables from cores of a cat5 cable to a shielded alternative.
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Moving the PSU cables away from the unshielded signal softened the low frequency peaks. There are still multiple's op 50Hz to be seen on the spectrum. However, so are on the pc->pre->pc loop.
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post39,
The PCB layout shows five tappings into the Power Ground between the two main decoupling capacitors.
Every one of those five tappings will pick off a different voltage and use ithat differing voltage as if it were a reference to zero Volts.
That PCB can never perform well.
The PCB layout shows five tappings into the Power Ground between the two main decoupling capacitors.
Every one of those five tappings will pick off a different voltage and use ithat differing voltage as if it were a reference to zero Volts.
That PCB can never perform well.
How can I enhance the ground layout according to you? I thought that putting the layout in a star like this was ok. If I need more local decoupling near the star, that's an easy fix. Should I put decoupling caps from +V and -V near the star?
Let's get you thinking about the basics.
When a current passes from +ve decoupling ground to Power Ground and when current passes from -ve decoupling ground to Power Ground there will be a voltage drop along the trace joining these decoupling capacitors together. Do you understand that?
That current can be DC or AC or individual pulses. These different currents will create a voltage drop along the trace. Do you understand that?
Looking at the area of the trace around the Power Ground. Any part of the trace that is at a different position will be at a different voltage from any other part. Do you understand that?
Look at the five tappings into the Power Ground. Are they all at the same reference voltage?
When a current passes from +ve decoupling ground to Power Ground and when current passes from -ve decoupling ground to Power Ground there will be a voltage drop along the trace joining these decoupling capacitors together. Do you understand that?
That current can be DC or AC or individual pulses. These different currents will create a voltage drop along the trace. Do you understand that?
Looking at the area of the trace around the Power Ground. Any part of the trace that is at a different position will be at a different voltage from any other part. Do you understand that?
Look at the five tappings into the Power Ground. Are they all at the same reference voltage?
But there is no way of connecting every grounded component to ground without some sort of wire/track right? I understand what you are telling me but fixing it is the problem.
Separate Signal Ground from Power Ground.
Connect the decoupling capacitors together so that the total circuit length is minimised.
I'd suggest a total circuit length including the cap pin pitch for the HF decoupling be <20mm.
And <60mm for the MF decoupling.
You need to start again.
Connect the decoupling capacitors together so that the total circuit length is minimised.
I'd suggest a total circuit length including the cap pin pitch for the HF decoupling be <20mm.
And <60mm for the MF decoupling.
You need to start again.
Do you perhaps have an example of a class AB amplifier layout that has a well implemented ground-layout as an example?
If I understand you correctly this is better? On top, Powerground, On bottom, Signalground, connected by a track on the right.
If I understand you correctly this is better? On top, Powerground, On bottom, Signalground, connected by a track on the right.
An externally hosted image should be here but it was not working when we last tested it.
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And with a proper PSU, thats better, noise dropped below -100dBu. Only 200Hz and 250Hz still pop out. 250Hz is in my reference loop too so that contribution is not due to the amplifier.
An externally hosted image should be here but it was not working when we last tested it.
Look at the hum and buzz. Most of that is due to connecting your 5 tappings into different voltages.
Some of it is due to connecting the Signal Ground to the Power Ground.
Some of it is due to connecting the Signal Ground to the Power Ground.
Is the idead behind the layout from post 50 correct?
http://www.diyaudio.com/forums/solid-state/212342-esp-p3a-layout-5.html#post3040926
http://www.diyaudio.com/forums/solid-state/212342-esp-p3a-layout-5.html#post3040926
I cannot make out what is happening under/over Q7. I'm guessing the other device is Q8.
Six displaced tappings in that ground is worse then five.
Six displaced tappings in that ground is worse then five.
Take a look at the PCB in the attachment of post #188 in this thread:
diyAB Amp - The "Honey Badger"
This PCB layout has been developed by several experienced members and might well serve as a guide.
Well it's hard to keep the ground traces close and short, while I was advised earlier to keep the power and voltage stage far apart.....
In the picture below all high current stuff is at the top half of the pcb en the low current components are on the lower half. Top two connectors are for power and ls gnd.
The components above Q7 and Q8 can be placed there since the transistors go underneath the pcb.
In the picture below all high current stuff is at the top half of the pcb en the low current components are on the lower half. Top two connectors are for power and ls gnd.
The components above Q7 and Q8 can be placed there since the transistors go underneath the pcb.
An externally hosted image should be here but it was not working when we last tested it.
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A couple of points I can see:
1) The signal ground trace running up the RH side of the board meets with two decoupling capacitors before reaching the 0V terminal point. As AndrewT stated in post #47: "When a current passes from +ve decoupling ground to Power Ground and when current passes from -ve decoupling ground to Power Ground there will be a voltage drop along the trace joining these decoupling capacitors together". You are sharing a section of this trace between signal ground and the rail decoupling. My suggestion would be to join the signal ground trace to a point nearer to the 0V terminal, even if it has to travel slightly further. Keep this trace separate to that which connects to the decoupling caps.
2) You have thick traces connecting the emitters of the output transistors to the rails, yet thinner ones connect their collectors to R13, R14. The amount of current will be nearly the same between the collectors and emitters.
1) The signal ground trace running up the RH side of the board meets with two decoupling capacitors before reaching the 0V terminal point. As AndrewT stated in post #47: "When a current passes from +ve decoupling ground to Power Ground and when current passes from -ve decoupling ground to Power Ground there will be a voltage drop along the trace joining these decoupling capacitors together". You are sharing a section of this trace between signal ground and the rail decoupling. My suggestion would be to join the signal ground trace to a point nearer to the 0V terminal, even if it has to travel slightly further. Keep this trace separate to that which connects to the decoupling caps.
2) You have thick traces connecting the emitters of the output transistors to the rails, yet thinner ones connect their collectors to R13, R14. The amount of current will be nearly the same between the collectors and emitters.
Also "C+1" 100nF near to Q2, another rail decoupling capacitor, decouples V+ to signal ground. Not a good idea!
@SuperR,
a typical layout of mine looks like this:
and follows these guidelines:
- the positive power-rail is on the left side, the negative one on the right side
- the power caps are placed as near as possible to the output capacitors
- the taps to the power-rails for the frontend lie immediately behind the fuseholders
- the signalGND is tapped from the power-GND connector
I hope that this picture inspires your current work.
Best regards - Rudi_Ratlos
a typical layout of mine looks like this:
and follows these guidelines:
- the positive power-rail is on the left side, the negative one on the right side
- the power caps are placed as near as possible to the output capacitors
- the taps to the power-rails for the frontend lie immediately behind the fuseholders
- the signalGND is tapped from the power-GND connector
I hope that this picture inspires your current work.
Best regards - Rudi_Ratlos
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