ES9038Q2M Board

You need two dual opamps. The Victor schematic is only for one channel. Each dac channel has two dac outputs, inverting and non-inverting. There is also one AVCC power input pin for each channel, and one (+1.65v) opamp common mode reference for each dac channel.

The opamps should be OPA1612 from an honest seller, such as Mouser or Digikey.

You might want to take a look at the ES9038Q2M datasheet which can be downloaded from Mouser.

Also I will attach below the schematic for the ES9038Q2M evaluation board, in case that helps. You can see there are two dual opamps for the output stage. There are also two opamp buffers, one for AVCC_L and one for AVCC_R. The output stage design used in the evaluation board is for balanced outputs. OTOH, Victor's schematic is for unbalanced outputs.
 

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Guys, can upload a current photos of the mod? I saw a few photos but is there a difference between them.

Probably I can't find a two same 1612 (rare) so I want try mod with current opamp without big changes. Is it possible?
It's a little difficult for me to add one more opamp correctly in scheme.
 
Guys, can upload a current photos of the mod?
There is not just one mod. There are various ways to make a better output stage. As for Victor's circuit, I never saw a pic of how he laid it out. All I have is the schematic already posted.
Probably I can't find a two same 1612 (rare) so I want try mod with current opamp without big changes.
That's what everyone wanted.
Is it possible?
Not really.
It's a little difficult for me to add one more opamp correctly in scheme.
Exactly. Now you are starting to see just how bad this board design is. The only place there is space for an output stage is on the back side of the board. Not on the top side.
There are various construction techniques that can be used to build an output stage there, or else attach another board there to extend the ground plane. That's why I said before that fixing this dac board is a lot of work. I also said there is no easy fix just by replacing a few parts. Its appears that you are just starting to understand what I meant when I said those things. Also, other people have been trying to tell you the same kinds of things in terms of their own experience.

Again, we would have been happy to tell you about all these things if you had asked first before getting the board. Now that you have it you need to decide what you want to do. Do you want to do a lot of work and learn about laying out dac output stages, or do you just want an easy dac project at a low price? If its the latter thing you want, then this board is not right one. Maybe you should consider it a loss and move on?
 
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IIRC some people tried that output stage. Don't recall most of them getting it to work properly/satisfactorily, although looks like oversimon was satisfied in that one case. It was listed in one of the old ESS documents I already posted, but IIUC that document is from back in the time where ESS was just starting out. ES9018 may have been their best dac at the time, or maybe something even older. Could be the circuit worked better with those dacs, don't know.
 
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Yes. There have been various comments on that. The settings would be different for every sample rate, etc. Some people think the chip sounds 'better' with THD compensation turned off. However it is possible to tweak 2nd and 3rd HD to make numbers look better. Unfortunately, 2nd and 3rd are the least objectionable. May also depend on what frequency you use to optimize the settings. That said, since Benchmark DAC-3 upsamples all PCM to something like 211kHz, they only have to tweak HD compensation for one sample rate (which they do in the factory for each individual dac).
 
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Has anyone evaluated the effectiveness of the "THD Compensation" feature as described on page 11 of the ES9038Q2M data sheet rev.1.4?
It is close to impossible to reach datasheet performance without using THD compensation. Balanced output stages tend to have elevated 3rd harmonic and THD compensation can be effectively used to lower that. Here is an example with only 3rd HD compensated. However THD compensation of ES9038Q2M is slightly crippled as it is common to both channels so it works best in dual mono configuration (as in the link). The newer ES9039Q2M has channel specific THD compensation. What I find problematic with ES9038Q2M is that THD is very dependent on level. Even tiny 0.1dB changes in level can change THD by several dBs. But if THD is below -120dB these variations are likely not audible.
Some people think the chip sounds 'better' with THD compensation turned off.
And some people think the opposite. Even though 2nd and 3rd harmonics are mostly benign they will also result in IMD. And the basic flaw of ES9038Q2M (i.e. highly level-dependent THD) is there even if THD compensation is not used.
 
Dac should be able to figure out correct number of bits from comparing BCLK frequency to LRCK frequency. What are the clock frequencies you measure for 16-bits?
not true, sabre32s seems to auto-detect 24-32bit i2s and dsd when playing 16-bit i2s files forcing a register reset otherwise there will be horrible boiling distortion. This is why dacs that use sabre32 often use SCR . converter chips
 
I said it should be able to figure it out, didn't say it does figure it out correctly. Did you measure the BCLK and LRCK frequencies or not?
I have studied some scenarios of sabre32 DAC, if running just usb they will use xmos to communicate i2c with dac, now xmos will rely on its output signal to set registers for sabre32 to understand it needs What mode should it be in? In contrast to multi-input DACs they will use an SRC chip the task of this SRC is to recognize the input and set the register for sabre32 or even this SRC to recognize the input connvert output to i2s 32bit or DSD256/ 512
 
auto input doesn't seem to support i2s 16bit
That is correct. Serial data length needs to be set separately in ESS dacs. Whether this is an issue depends on how the incoming I2S signal is generated. With I2S there is no need to use 32-bit frames (i.e 16-bits per channel) for 16-bit data as the frame length could be 64-bits regardless of serial data length (16/24/32 bits). For 16- or 24-bit data lower bits would just be set to zero. In this way the dac always operates with 32-bit serial data length and auto input works without problems.
 
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That is correct. Serial data length needs to be set separately in ESS dacs. Whether this is an issue depends on how the incoming I2S signal is generated. With I2S there is no need to use 32-bit frames (i.e 16-bits per channel) for 16-bit data as the frame length could be 64-bits regardless of serial data length (16/24/32 bits). For 16- or 24-bit data lower bits would just be set to zero. In this way the dac always operates with 32-bit serial data length and auto input works without problems.
i am learning about SRC to fix this problem, do you have any suggestion on this? What is the chip used in these machines?
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